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Ciro Santilli 六四事件 法轮功
2019-09-05 00:00:00 +00:00
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@@ -1175,12 +1175,18 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
<li><a href="#gem5-clang-build">18.15.2. gem5 clang build</a></li>
<li><a href="#gem5-sanitation-build">18.15.3. gem5 sanitation build</a></li>
<li><a href="#gem5-ruby-build">18.15.4. gem5 Ruby build</a></li>
<li><a href="#gem5-python-3-build">18.15.5. gem5 Python 3 build</a></li>
</ul>
</li>
<li><a href="#gem5-arm-platforms">18.16. gem5 ARM platforms</a></li>
<li><a href="#gem5-internals">18.17. gem5 internals</a>
<li><a href="#gem5-cpu-types">18.16. gem5 CPU types</a>
<ul class="sectlevel3">
<li><a href="#gem5-python-c-interaction">18.17.1. gem5 Python C++ interaction</a></li>
<li><a href="#gem5-arm-rsk">18.16.1. gem5 ARM RSK</a></li>
</ul>
</li>
<li><a href="#gem5-arm-platforms">18.17. gem5 ARM platforms</a></li>
<li><a href="#gem5-internals">18.18. gem5 internals</a>
<ul class="sectlevel3">
<li><a href="#gem5-python-c-interaction">18.18.1. gem5 Python C++ interaction</a></li>
</ul>
</li>
</ul>
@@ -3689,7 +3695,7 @@ echo "$(./getvar --arch aarch64 --emulator gem5 image)"</pre>
</div>
</div>
<div class="paragraph">
<p>see also: <a href="#gem5-arm-platforms">Section 18.16, &#8220;gem5 ARM platforms&#8221;</a>.</p>
<p>see also: <a href="#gem5-arm-platforms">Section 18.17, &#8220;gem5 ARM platforms&#8221;</a>.</p>
</div>
<div class="paragraph">
<p>This generates yet new separate images with new magic constants:</p>
@@ -20069,7 +20075,8 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
</div>
<div class="literalblock">
<div class="content">
<pre>./build-gem5 --arch aarch64 --gem5-build-id ruby -- PROTOCOL=MESI_Two_Level</pre>
<pre>./build-gem5 --arch aarch64 --gem5-build-id ruby -- PROTOCOL=MESI_Two_Level
./run --arch aarch64 --emulator -gem5 --gem5-build-id ruby -- --ruby</pre>
</div>
</div>
<div class="paragraph">
@@ -20106,9 +20113,71 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
<p>A minimized ruby config which was not merged upstream can be found for study at: <a href="https://gem5-review.googlesource.com/c/public/gem5/+/13599/1" class="bare">https://gem5-review.googlesource.com/c/public/gem5/+/13599/1</a></p>
</div>
</div>
<div class="sect3">
<h4 id="gem5-python-3-build"><a class="anchor" href="#gem5-python-3-build"></a><a class="link" href="#gem5-python-3-build">18.15.5. gem5 Python 3 build</a></h4>
<div class="paragraph">
<p>Python 3 support was mostly added in 2019 Q3 at arounda347a1a68b8a6e370334be3a1d2d66675891e0f1 but remained buggy for some time afterwards.</p>
</div>
<div class="paragraph">
<p>In an Ubuntu 18.04 host where <code>python</code> is <code>python2</code> by default, build with Python 3 instead with:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>./build-gem5 --gem5-build-id python3 -- PYTHON_CONFIG=python3-config</pre>
</div>
</div>
<div class="paragraph">
<p>Python 3 is then automatically used when running if you use that build.</p>
</div>
</div>
</div>
<div class="sect2">
<h3 id="gem5-arm-platforms"><a class="anchor" href="#gem5-arm-platforms"></a><a class="link" href="#gem5-arm-platforms">18.16. gem5 ARM platforms</a></h3>
<h3 id="gem5-cpu-types"><a class="anchor" href="#gem5-cpu-types"></a><a class="link" href="#gem5-cpu-types">18.16. gem5 CPU types</a></h3>
<div class="paragraph">
<p>gem5 has a few in tree CPU models for different purposes, here is an overview of the most interesting ones:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>BaseSimpleCPU</code> descendants. Have no CPU pipeline.</p>
<div class="ulist">
<ul>
<li>
<p><code>AtomicSimpleCPU</code>: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to <a href="#gem5-restore-checkpoint-with-a-different-cpu">gem5 restore checkpoint with a different CPU</a>.</p>
</li>
<li>
<p><code>TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU</code>. TODO: application?</p>
</li>
</ul>
</div>
</li>
<li>
<p><code>MinorCPU</code>: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <a href="#gem5-arm-rsk">gem5 ARM RSK</a>.</p>
<div class="ulist">
<ul>
<li>
<p><code>HPI</code>: derived from <code>MinorCPU</code> simply by parametrization. According to <a href="#gem5-arm-rsk">gem5 ARM RSK</a>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."</p>
</li>
</ul>
</div>
</li>
<li>
<p><code>DerivO3CPU</code>: out-of-order core</p>
</li>
</ul>
</div>
<div class="sect3">
<h4 id="gem5-arm-rsk"><a class="anchor" href="#gem5-arm-rsk"></a><a class="link" href="#gem5-arm-rsk">18.16.1. gem5 ARM RSK</a></h4>
<div class="paragraph">
<p><a href="https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf" class="bare">https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf</a></p>
</div>
<div class="paragraph">
<p>Dated 2017, it contains a good overview of gem5 CPUs.</p>
</div>
</div>
</div>
<div class="sect2">
<h3 id="gem5-arm-platforms"><a class="anchor" href="#gem5-arm-platforms"></a><a class="link" href="#gem5-arm-platforms">18.17. gem5 ARM platforms</a></h3>
<div class="paragraph">
<p>The gem5 platform is selectable with the <code>--machine</code> option, which is named after the analogous QEMU <code>-machine</code> option, and which sets the <code>--machine-type</code>.</p>
</div>
@@ -20136,9 +20205,9 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
</div>
</div>
<div class="sect2">
<h3 id="gem5-internals"><a class="anchor" href="#gem5-internals"></a><a class="link" href="#gem5-internals">18.17. gem5 internals</a></h3>
<h3 id="gem5-internals"><a class="anchor" href="#gem5-internals"></a><a class="link" href="#gem5-internals">18.18. gem5 internals</a></h3>
<div class="sect3">
<h4 id="gem5-python-c-interaction"><a class="anchor" href="#gem5-python-c-interaction"></a><a class="link" href="#gem5-python-c-interaction">18.17.1. gem5 Python C++ interaction</a></h4>
<h4 id="gem5-python-c-interaction"><a class="anchor" href="#gem5-python-c-interaction"></a><a class="link" href="#gem5-python-c-interaction">18.18.1. gem5 Python C++ interaction</a></h4>
<div class="paragraph">
<p>The interaction uses the Python C extension interface <a href="https://docs.python.org/2/extending/extending.html" class="bare">https://docs.python.org/2/extending/extending.html</a> interface through the pybind11 helper library: <a href="https://github.com/pybind/pybind11" class="bare">https://github.com/pybind/pybind11</a></p>
</div>
@@ -22042,8 +22111,24 @@ When instructions do not interpret this operand encoding as the zero register, u
</div>
</div>
<div class="paragraph">
<p>or in one go with <a href="#tmux">tmux</a>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>./run \
--arch aarch64 \
--gdb-wait \
--tmux-args=--no-continue \
--userland userland/arch/aarch64/freestanding/linux/hello.S \
;</pre>
</div>
</div>
<div class="paragraph">
<p>You are now left on the very first instruction of our tiny executable!</p>
</div>
<div class="paragraph">
<p>This is analogous to <a href="#baremetal-gdb-step-debug">step debugging baremetal examples</a>.</p>
</div>
<div class="sect4">
<h5 id="nostartfiles-programs"><a class="anchor" href="#nostartfiles-programs"></a><a class="link" href="#nostartfiles-programs">21.5.1.1. nostartfiles programs</a></h5>
<div class="paragraph">
@@ -25949,10 +26034,13 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.</p>
<div class="sect3">
<h4 id="arm-sve"><a class="anchor" href="#arm-sve"></a><a class="link" href="#arm-sve">23.6.5. ARM SVE</a></h4>
<div class="paragraph">
<p>Scalable Vector Extension.</p>
</div>
<div class="paragraph">
<p>Example: <a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/userland/arch/aarch64/sve.S">userland/arch/aarch64/sve.S</a></p>
</div>
<div class="paragraph">
<p>Scalable Vector Extension.</p>
<p>To understand it, the first thing you have to look at is the execution example at Fig 1 of: <a href="https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf" class="bare">https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf</a></p>
</div>
<div class="paragraph">
<p>aarch64 only, newer than <a href="#arm-neon">ARM NEON</a>.</p>
@@ -25961,10 +26049,20 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.</p>
<p>It is called Scalable because it does not specify the vector width! Therefore we don&#8217;t have to worry about new vector width instructions every few years! Hurray!</p>
</div>
<div class="paragraph">
<p>The instructions then allow implicitly tracking the loop index without knowing the actual vector length.</p>
<p>The instructions then allow:</p>
</div>
<div class="ulist">
<ul>
<li>
<p>incrementing loop index by the vector length without explicitly hardcoding it</p>
</li>
<li>
<p>when the last loop is reached, extra bytes that are not multiples of the vector length get automatically masked out by the predicate register, and have no effect</p>
</li>
</ul>
</div>
<div class="paragraph">
<p>Added to QEMU use mode in 3.0.0.</p>
<p>Added to QEMU in 3.0.0 and gem5 in 2019 Q3.</p>
</div>
<div class="paragraph">
<p>TODO announcement date. Possibly 2017: <a href="https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf" class="bare">https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf</a> There is also a 2016 mention: <a href="https://community.arm.com/tools/hpc/b/hpc/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture" class="bare">https://community.arm.com/tools/hpc/b/hpc/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture</a></p>
@@ -25989,9 +26087,6 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.</p>
<p><a href="https://www.rico.cat/files/ICS18-gem5-sve-tutorial.pdf" class="bare">https://www.rico.cat/files/ICS18-gem5-sve-tutorial.pdf</a> step by step of a complete code execution examples, the best initial tutorial so far</p>
</li>
<li>
<p><a href="https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf" class="bare">https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf</a> paper with some nice few concrete examples, illustrations and rationale</p>
</li>
<li>
<p><a href="https://static.docs.arm.com/dui0965/c/DUI0965C_scalable_vector_extension_guide.pdf" class="bare">https://static.docs.arm.com/dui0965/c/DUI0965C_scalable_vector_extension_guide.pdf</a></p>
</li>
<li>
@@ -26313,6 +26408,9 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.</p>
</div>
</div>
<div class="paragraph">
<p>analogously to what is done for <a href="#freestanding-programs">Freestanding programs</a>.</p>
</div>
<div class="paragraph">
<p>Now you can just <code>stepi</code> to when jumping into main to go to the C code in <a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/userland/c/hello.c">userland/c/hello.c</a>.</p>
</div>
<div class="paragraph">