diff --git a/index.html b/index.html index 595e1c3..188d858 100644 --- a/index.html +++ b/index.html @@ -1175,12 +1175,18 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
  • 18.15.2. gem5 clang build
  • 18.15.3. gem5 sanitation build
  • 18.15.4. gem5 Ruby build
    • +
  • 18.15.5. gem5 Python 3 build
    • -
  • 18.16. gem5 ARM platforms
    • -
  • 18.17. gem5 internals +
  • 18.16. gem5 CPU types +
    • +
  • 18.17. gem5 ARM platforms
    • +
  • 18.18. gem5 internals +
    • @@ -3689,7 +3695,7 @@ echo "$(./getvar --arch aarch64 --emulator gem5 image)"
    -

    see also: Section 18.16, “gem5 ARM platforms”.

    +

    see also: Section 18.17, “gem5 ARM platforms”.

    This generates yet new separate images with new magic constants:

    @@ -20069,7 +20075,8 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
    -
    ./build-gem5 --arch aarch64 --gem5-build-id ruby -- PROTOCOL=MESI_Two_Level
    +
    ./build-gem5 --arch aarch64 --gem5-build-id ruby -- PROTOCOL=MESI_Two_Level
+./run --arch aarch64 --emulator -gem5 --gem5-build-id ruby -- --ruby
    @@ -20106,9 +20113,71 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:

    A minimized ruby config which was not merged upstream can be found for study at: https://gem5-review.googlesource.com/c/public/gem5/+/13599/1

    +
    +

    18.15.5. gem5 Python 3 build

    +
    +

    Python 3 support was mostly added in 2019 Q3 at arounda347a1a68b8a6e370334be3a1d2d66675891e0f1 but remained buggy for some time afterwards.

    +
    +
    +

    In an Ubuntu 18.04 host where python is python2 by default, build with Python 3 instead with:

    +
    +
    +
    +
    ./build-gem5 --gem5-build-id python3 -- PYTHON_CONFIG=python3-config
    +
    +
    +
    +

    Python 3 is then automatically used when running if you use that build.

    +
    +
    -

    18.16. gem5 ARM platforms

    +

    18.16. gem5 CPU types

    +
    +

    gem5 has a few in tree CPU models for different purposes, here is an overview of the most interesting ones:

    +
    +
    + +
    +
    +

    18.16.1. gem5 ARM RSK

    +
    +

    https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf

    +
    +
    +

    Dated 2017, it contains a good overview of gem5 CPUs.

    +
    +
    +
    +
    +

    18.17. gem5 ARM platforms

    The gem5 platform is selectable with the --machine option, which is named after the analogous QEMU -machine option, and which sets the --machine-type.

    @@ -20136,9 +20205,9 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
    -

    18.17. gem5 internals

    +

    18.18. gem5 internals

    -

    18.17.1. gem5 Python C++ interaction

    +

    18.18.1. gem5 Python C++ interaction

    The interaction uses the Python C extension interface https://docs.python.org/2/extending/extending.html interface through the pybind11 helper library: https://github.com/pybind/pybind11

    @@ -22042,8 +22111,24 @@ When instructions do not interpret this operand encoding as the zero register, u
    +

    or in one go with tmux:

    +
    +
    +
    +
    ./run \
+  --arch aarch64 \
+  --gdb-wait \
+  --tmux-args=--no-continue \
+  --userland userland/arch/aarch64/freestanding/linux/hello.S \
+;
    +
    +
    +

    You are now left on the very first instruction of our tiny executable!

    +
    +

    This is analogous to step debugging baremetal examples.

    +
    21.5.1.1. nostartfiles programs
    @@ -25949,10 +26034,13 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.

    23.6.5. ARM SVE

    +

    Scalable Vector Extension.

    +
    +

    Example: userland/arch/aarch64/sve.S

    -

    Scalable Vector Extension.

    +

    To understand it, the first thing you have to look at is the execution example at Fig 1 of: https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf

    aarch64 only, newer than ARM NEON.

    @@ -25961,10 +26049,20 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.

    It is called Scalable because it does not specify the vector width! Therefore we don’t have to worry about new vector width instructions every few years! Hurray!

    -

    The instructions then allow implicitly tracking the loop index without knowing the actual vector length.

    +

    The instructions then allow:

    +
    +
    +
      +
    • +

      incrementing loop index by the vector length without explicitly hardcoding it

      +
      • +
    • +

      when the last loop is reached, extra bytes that are not multiples of the vector length get automatically masked out by the predicate register, and have no effect

      +
      • +
    -

    Added to QEMU use mode in 3.0.0.

    +

    Added to QEMU in 3.0.0 and gem5 in 2019 Q3.

    TODO announcement date. Possibly 2017: https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf There is also a 2016 mention: https://community.arm.com/tools/hpc/b/hpc/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture

    @@ -25989,9 +26087,6 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.

    https://www.rico.cat/files/ICS18-gem5-sve-tutorial.pdf step by step of a complete code execution examples, the best initial tutorial so far

  • -

    https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf paper with some nice few concrete examples, illustrations and rationale

    -
    • -

  • https://static.docs.arm.com/dui0965/c/DUI0965C_scalable_vector_extension_guide.pdf

  • @@ -26313,6 +26408,9 @@ AArch64, see Procedure Call Standard for the ARM 64-bit Architecture.

    • +

    analogously to what is done for Freestanding programs.

    +
    +

    Now you can just stepi to when jumping into main to go to the C code in userland/c/hello.c.