3rd-party/linux-kernel-module-cheat
1
0
Fork 0
mirror of https://github.com/cirosantilli/linux-kernel-module-cheat.git synced 2026-01-25 11:11:35 +01:00
Code Issues Releases Wiki Activity

1e93fdfe632bfdec51b84b6d9670ba3ef13639db

Browse Source
This commit is contained in:
Ciro Santilli 六四事件 法轮功
2019-10-25 00:00:00 +00:00
parent 95051297c9
commit a5a77534c7
1 changed files with 118 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

149
index.html
View File

@@ -1185,7 +1185,10 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
</li>
<li><a href="#gem5-cpu-types">19.17. gem5 CPU types</a>
<ul class="sectlevel3">
<li><a href="#gem5-arm-rsk">19.17.1. gem5 ARM RSK</a></li>
<li><a href="#gem5-basesimplecpu">19.17.1. gem5 BaseSimpleCPU</a></li>
<li><a href="#gem5-minorcpu">19.17.2. gem5 MinorCPU</a></li>
<li><a href="#gem5-deriveo3cpu">19.17.3. gem5 DeriveO3CPU</a></li>
<li><a href="#gem5-arm-rsk">19.17.4. gem5 ARM RSK</a></li>
</ul>
</li>
<li><a href="#gem5-arm-platforms">19.18. gem5 ARM platforms</a></li>
@@ -20338,40 +20341,124 @@ Indirect leak of 1346 byte(s) in 2 object(s) allocated from:
<div class="sect2">
<h3 id="gem5-cpu-types"><a class="anchor" href="#gem5-cpu-types"></a><a class="link" href="#gem5-cpu-types">19.17. gem5 CPU types</a></h3>
<div class="paragraph">
<p>gem5 has a few in tree CPU models for different purposes. In fs.py and se.py, those are selectable with the <code>--cpu-type</code> option. Here is an overview of the most interesting ones:</p>
<p>gem5 has a few in tree CPU models for different purposes.</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>BaseSimpleCPU</code> descendants. Have no CPU pipeline.</p>
<div class="ulist">
<ul>
<li>
<p><code>AtomicSimpleCPU</code>: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to <a href="#gem5-restore-checkpoint-with-a-different-cpu">gem5 restore checkpoint with a different CPU</a>.</p>
</li>
<li>
<p><code>TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU</code>. TODO: application?</p>
</li>
</ul>
<div class="paragraph">
<p>In fs.py and se.py, those are selectable with the <code>--cpu-type</code> option.</p>
</div>
</li>
<li>
<p><code>MinorCPU</code>: in-order core. The weird name "Minor" stands for "M (TODO what is M) IN ONder". Its 4 stage pipeline is described at the "MinorCPU" section of <a href="#gem5-arm-rsk">gem5 ARM RSK</a>. As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of <a href="https://en.wikipedia.org/wiki/ARM_big.LITTLE">ARM bigLITTLE</a>.</p>
<div class="ulist">
<ul>
<li>
<p><code>HPI</code>: derived from <code>MinorCPU</code> simply by parametrization. According to <a href="#gem5-arm-rsk">gem5 ARM RSK</a>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."</p>
</li>
</ul>
</div>
</li>
<li>
<p><code>DerivO3CPU</code>: out-of-order core. "O3" Stands for "Out Of Order"!</p>
</li>
</ul>
<div class="paragraph">
<p>TODO are there any public performance correlations between those models and real cores?</p>
</div>
<div class="sect3">
<h4 id="gem5-arm-rsk"><a class="anchor" href="#gem5-arm-rsk"></a><a class="link" href="#gem5-arm-rsk">19.17.1. gem5 ARM RSK</a></h4>
<h4 id="gem5-basesimplecpu"><a class="anchor" href="#gem5-basesimplecpu"></a><a class="link" href="#gem5-basesimplecpu">19.17.1. gem5 BaseSimpleCPU</a></h4>
<div class="paragraph">
<p>Simple abstract CPU without a pipeline.</p>
</div>
<div class="paragraph">
<p>Implementations:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>AtomicSimpleCPU</code>: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all.</p>
<div class="paragraph">
<p>Useful to <a href="#gem5-restore-checkpoint-with-a-different-cpu">boot Linux fast and then checkpoint and switch to a more detailed CPU</a>.</p>
</div>
</li>
<li>
<p><code>TimingSimpleCPU</code>: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than <code>AtomicSimpleCPU</code>. TODO: application?</p>
</li>
</ul>
</div>
</div>
<div class="sect3">
<h4 id="gem5-minorcpu"><a class="anchor" href="#gem5-minorcpu"></a><a class="link" href="#gem5-minorcpu">19.17.2. gem5 MinorCPU</a></h4>
<div class="paragraph">
<p>Generic in-order core that does not model any specific CPU.</p>
</div>
<div class="paragraph">
<p>Its C++ implementation that can be parametrized to more closely match real cores.</p>
</div>
<div class="paragraph">
<p>Note that since gem5 is highly parametrizable, the parametrization could even change which instructions a CPU can execute by altering its available <a href="https://en.wikipedia.org/wiki/Execution_unit">functional units</a>, which are used to model performance.</p>
</div>
<div class="paragraph">
<p>For example, <code>MinorCPU</code> allows all implemented instructions, including <a href="#arm-sve">ARM SVE</a> instructions, but a derived class modelling, say, an <a href="https://en.wikipedia.org/wiki/ARM_Cortex-A7">ARM Cortex A7 core</a>, might not, since SVE is a newer feature and the A7 core does not have SVE.</p>
</div>
<div class="paragraph">
<p>The weird name "Minor" stands for "M (TODO what is M) IN ONder".</p>
</div>
<div class="paragraph">
<p>Its 4 stage pipeline is described at the "MinorCPU" section of <a href="#gem5-arm-rsk">gem5 ARM RSK</a>.</p>
</div>
<div class="paragraph">
<p>As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of <a href="https://en.wikipedia.org/wiki/ARM_big.LITTLE">ARM bigLITTLE</a>.</p>
</div>
<div class="paragraph">
<p>The following models extend the <code>MinorCPU</code> class by parametrization to make it match existing CPUs more closely:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>HPI</code>: derived from <code>MinorCPU</code>.</p>
<div class="paragraph">
<p>Created by Ashkan Tousi in 2017 while working at ARM.</p>
</div>
<div class="paragraph">
<p>According to <a href="#gem5-arm-rsk">gem5 ARM RSK</a>:</p>
</div>
<div class="quoteblock">
<blockquote>
<div class="paragraph">
<p>The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation.</p>
</div>
</blockquote>
</div>
</li>
<li>
<p><code>ex5_LITTLE</code>: derived from <code>MinorCPU</code>. Description reads:</p>
<div class="quoteblock">
<blockquote>
<div class="paragraph">
<p>ex5 LITTLE core (based on the ARM Cortex-A7)</p>
</div>
</blockquote>
</div>
<div class="paragraph">
<p>Implemented by Pierre-Yves Péneau from LIRMM, which is a research lab in Montpellier, France, in 2017.</p>
</div>
</li>
</ul>
</div>
</div>
<div class="sect3">
<h4 id="gem5-deriveo3cpu"><a class="anchor" href="#gem5-deriveo3cpu"></a><a class="link" href="#gem5-deriveo3cpu">19.17.3. gem5 DeriveO3CPU</a></h4>
<div class="paragraph">
<p>Generic out-of-order core. "O3" Stands for "Out Of Order"!</p>
</div>
<div class="paragraph">
<p>Analogous to <a href="#gem5-minorcpu">MinorCPU</a>, but modelling an out of order core instead of in order.</p>
</div>
<div class="paragraph">
<p>Existing parametrizations:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>ex5_big</code>: big corresponding to <code>ex5_LITTLE</code>, by same author at same time. It description reads:</p>
<div class="quoteblock">
<blockquote>
<div class="paragraph">
<p>ex5 big core (based on the ARM Cortex-A15)</p>
</div>
</blockquote>
</div>
</li>
</ul>
</div>
</div>
<div class="sect3">
<h4 id="gem5-arm-rsk"><a class="anchor" href="#gem5-arm-rsk"></a><a class="link" href="#gem5-arm-rsk">19.17.4. gem5 ARM RSK</a></h4>
<div class="paragraph">
<p><a href="https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf" class="bare">https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf</a></p>
</div>