From a5a77534c757f20b7a635955db89d5c8210d9574 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ciro=20Santilli=20=E5=85=AD=E5=9B=9B=E4=BA=8B=E4=BB=B6=20?= =?UTF-8?q?=E6=B3=95=E8=BD=AE=E5=8A=9F?= Date: Fri, 25 Oct 2019 00:00:00 +0000 Subject: [PATCH] 1e93fdfe632bfdec51b84b6d9670ba3ef13639db --- index.html | 149 ++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 118 insertions(+), 31 deletions(-) diff --git a/index.html b/index.html index 0a87f7a..7543a70 100644 --- a/index.html +++ b/index.html @@ -1185,7 +1185,10 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
  • 19.17. gem5 CPU types
  • 19.18. gem5 ARM platforms
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    19.17. gem5 CPU types

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    gem5 has a few in tree CPU models for different purposes. In fs.py and se.py, those are selectable with the --cpu-type option. Here is an overview of the most interesting ones:

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    gem5 has a few in tree CPU models for different purposes.

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      BaseSimpleCPU descendants. Have no CPU pipeline.

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        AtomicSimpleCPU: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to gem5 restore checkpoint with a different CPU.

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        TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU. TODO: application?

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      In fs.py and se.py, those are selectable with the --cpu-type option.

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      MinorCPU: in-order core. The weird name "Minor" stands for "M (TODO what is M) IN ONder". Its 4 stage pipeline is described at the "MinorCPU" section of gem5 ARM RSK. As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of ARM bigLITTLE.

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        HPI: derived from MinorCPU simply by parametrization. According to gem5 ARM RSK: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."

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      DerivO3CPU: out-of-order core. "O3" Stands for "Out Of Order"!

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    TODO are there any public performance correlations between those models and real cores?

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    19.17.1. gem5 ARM RSK

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    19.17.1. gem5 BaseSimpleCPU

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    Simple abstract CPU without a pipeline.

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    Implementations:

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      AtomicSimpleCPU: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all.

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      Useful to boot Linux fast and then checkpoint and switch to a more detailed CPU.

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      TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than AtomicSimpleCPU. TODO: application?

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    19.17.2. gem5 MinorCPU

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    Generic in-order core that does not model any specific CPU.

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    Its C++ implementation that can be parametrized to more closely match real cores.

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    Note that since gem5 is highly parametrizable, the parametrization could even change which instructions a CPU can execute by altering its available functional units, which are used to model performance.

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    For example, MinorCPU allows all implemented instructions, including ARM SVE instructions, but a derived class modelling, say, an ARM Cortex A7 core, might not, since SVE is a newer feature and the A7 core does not have SVE.

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    The weird name "Minor" stands for "M (TODO what is M) IN ONder".

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    Its 4 stage pipeline is described at the "MinorCPU" section of gem5 ARM RSK.

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    As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of ARM bigLITTLE.

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    The following models extend the MinorCPU class by parametrization to make it match existing CPUs more closely:

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      HPI: derived from MinorCPU.

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      Created by Ashkan Tousi in 2017 while working at ARM.

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      According to gem5 ARM RSK:

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      The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation.

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      ex5_LITTLE: derived from MinorCPU. Description reads:

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      ex5 LITTLE core (based on the ARM Cortex-A7)

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      Implemented by Pierre-Yves Péneau from LIRMM, which is a research lab in Montpellier, France, in 2017.

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    19.17.3. gem5 DeriveO3CPU

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    Generic out-of-order core. "O3" Stands for "Out Of Order"!

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    Analogous to MinorCPU, but modelling an out of order core instead of in order.

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    Existing parametrizations:

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      ex5_big: big corresponding to ex5_LITTLE, by same author at same time. It description reads:

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      ex5 big core (based on the ARM Cortex-A15)

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    19.17.4. gem5 ARM RSK

    https://github.com/arm-university/arm-gem5-rsk/blob/aa3b51b175a0f3b6e75c9c856092ae0c8f2a7cdc/gem5_rsk.pdf