3rd-party/linux-kernel-module-cheat
1
0
Fork 0
mirror of https://github.com/cirosantilli/linux-kernel-module-cheat.git synced 2026-01-23 02:05:57 +01:00
Code Issues Releases Wiki Activity

gem5 cpu models: minor is low power

Browse Source
This commit is contained in:
Ciro Santilli 六四事件 法轮功
2019-09-07 00:00:02 +00:00
parent e38c9f2641
commit 986d6cfb7b
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
README.adoc
View File

@@ -12311,7 +12311,7 @@ gem5 has a few in tree CPU models for different purposes. In fs.py and se.py, th
* `BaseSimpleCPU` descendants. Have no CPU pipeline.
** `AtomicSimpleCPU`: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to <<gem5-restore-checkpoint-with-a-different-cpu>>.
** `TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application?
* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <<gem5-arm-rsk>>.
* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <<gem5-arm-rsk>>. As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of https://en.wikipedia.org/wiki/ARM_big.LITTLE[ARM bigLITTLE].
** `HPI`: derived from `MinorCPU` simply by parametrization. According to <<gem5-arm-rsk>>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."
* `DerivO3CPU`: out-of-order core. "O3" Stands for "Out Of Order"!