diff --git a/README.adoc b/README.adoc
index b4baca9..c8fbafd 100644
--- a/README.adoc
+++ b/README.adoc
@@ -12311,7 +12311,7 @@ gem5 has a few in tree CPU models for different purposes. In fs.py and se.py, th
 * `BaseSimpleCPU` descendants. Have no CPU pipeline.
 ** `AtomicSimpleCPU`: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to <<gem5-restore-checkpoint-with-a-different-cpu>>.
 ** `TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application?
-* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <<gem5-arm-rsk>>.
+* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <<gem5-arm-rsk>>. As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of https://en.wikipedia.org/wiki/ARM_big.LITTLE[ARM bigLITTLE].
 ** `HPI`: derived from `MinorCPU` simply by parametrization. According to <<gem5-arm-rsk>>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."
 * `DerivO3CPU`: out-of-order core. "O3" Stands for "Out Of Order"!