From 986d6cfb7bdd15dfda739e36fb91bccd9a040bd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ciro=20Santilli=20=E5=85=AD=E5=9B=9B=E4=BA=8B=E4=BB=B6=20?= =?UTF-8?q?=E6=B3=95=E8=BD=AE=E5=8A=9F?= Date: Sat, 7 Sep 2019 00:00:02 +0000 Subject: [PATCH] gem5 cpu models: minor is low power --- README.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index b4baca9..c8fbafd 100644 --- a/README.adoc +++ b/README.adoc @@ -12311,7 +12311,7 @@ gem5 has a few in tree CPU models for different purposes. In fs.py and se.py, th * `BaseSimpleCPU` descendants. Have no CPU pipeline. ** `AtomicSimpleCPU`: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all. Useful to <>. ** `TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application? -* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <>. +* `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <>. As of 2019, in-order cores are mostly present in low power / cost contexts, for example little cores of https://en.wikipedia.org/wiki/ARM_big.LITTLE[ARM bigLITTLE]. ** `HPI`: derived from `MinorCPU` simply by parametrization. According to <>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation." * `DerivO3CPU`: out-of-order core. "O3" Stands for "Out Of Order"!