o3 stands for out-of-order, OMG

README.adoc

@@ -10391,7 +10391,7 @@ Getting started at: xref:gem5-buildroot-setup[xrefstyle=full].
 === gem5 vs QEMU
 
 * advantages of gem5:
-** simulates a generic more realistic pipelined and optionally out of order CPU cycle by cycle, including a realistic DRAM memory access model with latencies, caches and page table manipulations. This allows us to:
+** simulates a generic more realistic <<gem5-cpu-models,optionally pipelined and out-of-order>> CPU cycle by cycle, including a realistic DRAM memory access model with latencies, caches and page table manipulations. This allows us to:
 +
 --
 *** do much more realistic performance benchmarking with it, which makes absolutely no sense in QEMU, which is purely functional
@@ -12313,7 +12313,7 @@ gem5 has a few in tree CPU models for different purposes, here is an overview of
 ** `TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application?
 * `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <<gem5-arm-rsk>>.
 ** `HPI`: derived from `MinorCPU` simply by parametrization. According to <<gem5-arm-rsk>>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation."
-* `DerivO3CPU`: out-of-order core
+* `DerivO3CPU`: out-of-order core. "O3" Stands for "Out Of Order"!
 
 ==== gem5 ARM RSK