From 906f7ac625e5060366df4325b3155904f9cf3a77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ciro=20Santilli=20=E5=85=AD=E5=9B=9B=E4=BA=8B=E4=BB=B6=20?= =?UTF-8?q?=E6=B3=95=E8=BD=AE=E5=8A=9F?= Date: Sat, 7 Sep 2019 00:00:00 +0000 Subject: [PATCH] o3 stands for out-of-order, OMG --- README.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.adoc b/README.adoc index d4e1be6..5110641 100644 --- a/README.adoc +++ b/README.adoc @@ -10391,7 +10391,7 @@ Getting started at: xref:gem5-buildroot-setup[xrefstyle=full]. === gem5 vs QEMU * advantages of gem5: -** simulates a generic more realistic pipelined and optionally out of order CPU cycle by cycle, including a realistic DRAM memory access model with latencies, caches and page table manipulations. This allows us to: +** simulates a generic more realistic <> CPU cycle by cycle, including a realistic DRAM memory access model with latencies, caches and page table manipulations. This allows us to: + -- *** do much more realistic performance benchmarking with it, which makes absolutely no sense in QEMU, which is purely functional @@ -12313,7 +12313,7 @@ gem5 has a few in tree CPU models for different purposes, here is an overview of ** `TimingSimpleCPU: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application? * `MinorCPU`: in-order core. Its 4 stage pipeline is described at the "MinorCPU" section of <>. ** `HPI`: derived from `MinorCPU` simply by parametrization. According to <>: "The HPI CPU timing model is tuned to be representative of a modern in-order Armv8-A implementation." -* `DerivO3CPU`: out-of-order core +* `DerivO3CPU`: out-of-order core. "O3" Stands for "Out Of Order"! ==== gem5 ARM RSK