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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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702 lines
40 KiB
HTML
702 lines
40 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. EVERYTHING is built from source. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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</head>
|
||
<body id="atomicsimplecpu-initial-events" class="article">
|
||
<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect5">
|
||
<h6 id="atomicsimplecpu-initial-events"><a class="anchor" href="#atomicsimplecpu-initial-events"></a><a class="link" href="#atomicsimplecpu-initial-events">24.22.4.1.1. AtomicSimpleCPU initial events</a></h6>
|
||
<div class="paragraph">
|
||
<p>Let’s have a closer look at the initial magically scheduled events of the simulation.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Most events come from other events, but at least one initial event must be scheduled somehow from elsewhere to kick things off.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The initial tick event:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>0: Event: AtomicSimpleCPU tick.wrapped_function_event: EventFunctionWrapped 39 scheduled @ 0</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>we’ll study by breaking at at the point that prints messages: <code>b Trace::OstreamLogger::logMessage()</code> to see where events are being scheduled from:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>Trace::OstreamLogger::logMessage() at trace.cc:149 0x5555593b3b1e
|
||
void Trace::Logger::dprintf_flag<char const*, char const*, unsigned long>() at 0x55555949e603
|
||
void Trace::Logger::dprintf<char const*, char const*, unsigned long>() at 0x55555949de58
|
||
Event::trace() at eventq.cc:395 0x55555946d109
|
||
EventQueue::schedule() at eventq_impl.hh:65 0x555557195441
|
||
EventManager::schedule() at eventq.hh:746 0x555557194aa2
|
||
AtomicSimpleCPU::activateContext() at atomic.cc:239 0x555559075531
|
||
SimpleThread::activate() at simple_thread.cc:177 0x555559545a63
|
||
Process::initState() at process.cc:283 0x555559484011
|
||
ArmProcess64::initState() at process.cc:126 0x55555730827a
|
||
ArmLinuxProcess64::initState() at process.cc:1,777 0x5555572d5e5e</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The interesting call is at <code>AtomicSimpleCPU::activateContext</code>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>schedule(tickEvent, clockEdge(Cycles(0)));</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which calls <code>EventManager::schedule</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p><code>AtomicSimpleCPU</code> is an <code>EventManager</code> because <a href="gem5-python-c-interaction.html"><code>SimObject</code></a> inherits from it.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p><code>tickEvent</code> is an <code>EventFunctionWrapper</code> which contains a <code>std::function<void(void)> callback;</code>, and is initialized in the constructor as:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
|
||
false, Event::CPU_Tick_Pri),</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The call stack above <code>ArmLinuxProcess64::initState</code> is <a href="pybind11.html">pybind11</a> fuzziness, but if we grep a bit we find the Python call point:</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>src/python/m5/simulate.py</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>def instantiate(ckpt_dir=None):
|
||
|
||
...
|
||
|
||
# Create the C++ sim objects and connect ports
|
||
for obj in root.descendants(): obj.createCCObject()
|
||
for obj in root.descendants(): obj.connectPorts()
|
||
|
||
# Do a second pass to finish initializing the sim objects
|
||
for obj in root.descendants(): obj.init()
|
||
|
||
...
|
||
|
||
# Restore checkpoint (if any)
|
||
if ckpt_dir:
|
||
...
|
||
else:
|
||
for obj in root.descendants(): obj.initState()</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and this gets called from the toplevel Python scripts e.g. se.py <code>configs/common/Simulation.py</code> does:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>m5.instantiate(checkpoint_dir)</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>As we can see, <code>initState</code> is just one stage of generic <code>SimObject</code> initialization. <code>root.descendants()</code> goes over the entire <code>SimObject</code> tree calling <code>initState()</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Finally, we see that <code>initState</code> is part of the <code>SimObject</code> C++ API:</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>src/sim/sim_object.hh</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>class SimObject : public EventManager, public Serializable, public Drainable,
|
||
public Stats::Group
|
||
{
|
||
|
||
...
|
||
|
||
/**
|
||
* initState() is called on each SimObject when *not* restoring
|
||
* from a checkpoint. This provides a hook for state
|
||
* initializations that are only required for a "cold start".
|
||
*/
|
||
virtual void initState();</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Finally, we see that <code>initState</code> is exposed to the Python API at:</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>build/ARM/python/_m5/param_SimObject.cc</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>module_init(py::module &m_internal)
|
||
{
|
||
py::module m = m_internal.def_submodule("param_SimObject");
|
||
py::class_<SimObjectParams, std::unique_ptr<SimObjectParams, py::nodelete>>(m, "SimObjectParams")
|
||
.def_readwrite("name", &SimObjectParams::name)
|
||
.def_readwrite("eventq_index", &SimObjectParams::eventq_index)
|
||
;
|
||
|
||
py::class_<SimObject, Drainable, Serializable, Stats::Group, std::unique_ptr<SimObject, py::nodelete>>(m, "SimObject")
|
||
.def("init", &SimObject::init)
|
||
.def("initState", &SimObject::initState)
|
||
.def("memInvalidate", &SimObject::memInvalidate)
|
||
.def("memWriteback", &SimObject::memWriteback)
|
||
.def("regProbePoints", &SimObject::regProbePoints)
|
||
.def("regProbeListeners", &SimObject::regProbeListeners)
|
||
.def("startup", &SimObject::startup)
|
||
.def("loadState", &SimObject::loadState, py::arg("cp"))
|
||
.def("getPort", &SimObject::getPort, pybind11::return_value_policy::reference, py::arg("if_name"), py::arg("idx"))
|
||
;
|
||
|
||
}</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which is more magical than the other param classes since <code>py::class_<SimObject</code> has non-trivial methods, those are auto-generated by the <code>cxx_exports</code> code generation mechanism:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>class SimObject(object):
|
||
|
||
...
|
||
|
||
cxx_exports = [
|
||
PyBindMethod("init"),
|
||
PyBindMethod("initState"),
|
||
PyBindMethod("memInvalidate"),
|
||
PyBindMethod("memWriteback"),
|
||
PyBindMethod("regProbePoints"),
|
||
PyBindMethod("regProbeListeners"),
|
||
PyBindMethod("startup"),
|
||
]</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And the second magically scheduled event is the exit event:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>0: Event: Event_70: generic 70 scheduled @ 0
|
||
0: Event: Event_70: generic 70 rescheduled @ 18446744073709551615</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which is scheduled with backtrace:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>Trace::OstreamLogger::logMessage() at trace.cc:149 0x5555593b3b1e
|
||
void Trace::Logger::dprintf_flag<char const*, char const*, unsigned long>() at 0x55555949e603
|
||
void Trace::Logger::dprintf<char const*, char const*, unsigned long>() at 0x55555949de58
|
||
Event::trace() at eventq.cc:395 0x55555946d109
|
||
EventQueue::schedule() at eventq_impl.hh:65 0x555557195441
|
||
BaseGlobalEvent::schedule() at global_event.cc:78 0x55555946d6f1
|
||
GlobalEvent::GlobalEvent() at 0x55555949d177
|
||
GlobalSimLoopExitEvent::GlobalSimLoopExitEvent() at sim_events.cc:61 0x555559474470
|
||
simulate() at simulate.cc:104 0x555559476d6f</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which comes at object creation inside <code>simulate()</code> through the <code>GlobalEvent()</code> constructor:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>simulate_limit_event =
|
||
new GlobalSimLoopExitEvent(mainEventQueue[0]->getCurTick(),
|
||
"simulate() limit reached", 0);</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This event indicates that the simulation should finish by overriding <code>bool isExitEvent()</code> which gets checked in the main simulation at <code>EventQueue::serviceOne</code>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>if (event->isExitEvent()) {
|
||
assert(!event->flags.isSet(Event::Managed) ||
|
||
!event->flags.isSet(Event::IsMainQueue)); // would be silly
|
||
return event;</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Tested in gem5 12c917de54145d2d50260035ba7fa614e25317a3.</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>↑ Up: <a href="gem5-event-queue-atomicsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="atomicsimplecpu-tick-reschedule-timing.html">AtomicSimpleCPU tick reschedule timing</a> →</p>
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