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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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62 lines
1.5 KiB
ArmAsm
62 lines
1.5 KiB
ArmAsm
/* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-loop-instruction-over-array */
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#include "common.h"
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#define NELEM 4
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#define ELEM_SIZE 4
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.data;
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my_array_0:
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.word 0x11111111, 0x22222222, 0x33333333, 0x44444444
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my_array_1:
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.word 0x55555555, 0x66666666, 0x77777777, 0x88888888
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ENTRY
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/* Load r5, r6, r7 and r8 starting from the address in r4. Don't change r4 */
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ldr r4, =my_array_0
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ldr r5, =0
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ldr r6, =0
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ldr r7, =0
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ldr r8, =0
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ldmia r4, {r5-r8}
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ASSERT_EQ(r4, my_array_0)
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ASSERT_EQ(r5, 0x11111111)
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ASSERT_EQ(r6, 0x22222222)
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ASSERT_EQ(r7, 0x33333333)
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ASSERT_EQ(r8, 0x44444444)
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/* Swapping the order of r5 and r6 on the mnemonic makes no difference to load order.
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*
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* But it gives an assembler warning, so we won't do it by default:
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*
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* ldmia.S: Assembler messages:
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* ldmia.S:32: Warning: register range not in ascending order
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*/
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#if 0
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ldr r4, =my_array_0
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ldr r5, =0
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ldr r6, =0
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ldmia r4, {r6,r5}
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ASSERT_EQ(r5, 0x11111111)
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ASSERT_EQ(r6, 0x22222222)
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#endif
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/* Modify the array */
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ldr r4, =my_array_1
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ldr r5, =0x55555555
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ldr r6, =0x66666666
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ldr r7, =0x77777777
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ldr r8, =0x88888888
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stmdb r4, {r5-r8}
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/* Verify that my_array_0 changed and is equal to my_array_1. */
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ASSERT_MEMCMP(my_array_0, my_array_1, 0x10)
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/* Load registers and increment r4. */
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ldr r4, =my_array_0
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ldmia r4!, {r5-r8}
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ASSERT_EQ(r4, my_array_1)
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EXIT
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