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gem5: document --fast-forward
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Ciro Santilli 六四事件 法轮功
175
README.adoc
175
README.adoc
@@ -11304,7 +11304,7 @@ info: Entering event queue @ 1000. Starting simulation...
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Exiting @ tick 2000 because m5_exit instruction encountered
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....
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and a similar thing happens for the restore with a different CPU type:
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and a similar thing happens for the <<gem5-restore-checkpoint-with-a-different-cpu,restore with a different CPU type>>:
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....
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info: Entering event queue @ 1000. Starting simulation...
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@@ -11442,24 +11442,185 @@ gem5 can switch to a different CPU model when restoring a checkpoint.
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A common combo is to boot Linux with a fast CPU, make a checkpoint and then replay the benchmark of interest with a slower CPU.
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An illustrative interactive run:
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This can be observed interactively in full system with:
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....
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./run --arch arm --emulator gem5
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./run --arch aarch64 --emulator gem5
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....
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In guest:
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Then in the guest terminal after boot ends:
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....
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m5 checkpoint
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sh -c 'm5 checkpoint;sh'
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m5 exit
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....
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And then restore the checkpoint with a different CPU:
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And then restore the checkpoint with a different slower CPU:
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....
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./run --arch arm --emulator gem5 --gem5-restore 1 -- --caches --restore-with-cpu=HPI
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./run --arch arm --emulator gem5 --gem5-restore 1 -- --caches --cpu-type=DerivO3CPU
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....
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And now you will notice that everything happens much slower in the guest terminal!
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One even more direct and minimal way to observe this is with link:userland/freestanding/gem5_checkpoint_restore.S[] which was mentioned at <<gem5-checkpoint-userland-minimal-example>> plus some logging:
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....
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./run \
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--arch aarch64 \
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--emulator gem5 \
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--static \
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--trace ExecAll,FmtFlag,O3CPU,SimpleCPU \
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--userland userland/freestanding/gem5_checkpoint_restore.S \
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;
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cat "$(./getvar --arch aarch64 --emulator gem5 trace_txt_file)"
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./run \
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--arch aarch64 \
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--emulator gem5 \
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--gem5-restore 1 \
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--static \
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--trace ExecAll,FmtFlag,O3CPU,SimpleCPU \
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--userland userland/freestanding/gem5_checkpoint_restore.S \
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-- \
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--caches \
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--cpu-type DerivO3CPU \
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--restore-with-cpu DerivO3CPU \
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;
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cat "$(./getvar --arch aarch64 --emulator gem5 trace_txt_file)"
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....
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At gem5 2235168b72537535d74c645a70a85479801e0651, the first run does everything in <<gem5-basesimplecpu,AtomicSimpleCPU>>:
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....
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...
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1f92 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e40 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e30 WriteReq
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0: SimpleCPU: system.cpu: Tick
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0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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500: SimpleCPU: system.cpu: Tick
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500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 : movz x1, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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1000: SimpleCPU: system.cpu: Tick
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1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 : m5checkpoint : IntAlu : flags=(IsInteger|IsNonSpeculative|IsUnverifiable)
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1000: SimpleCPU: system.cpu: Resume
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1500: SimpleCPU: system.cpu: Tick
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1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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2000: SimpleCPU: system.cpu: Tick
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2000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+16 : m5exit : No_OpClass : flags=(IsInteger|IsNonSpeculative)
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....
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and after restore we see as expected a single `ExecEnable` instruction executed amidst `O3CPU` noise:
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....
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FullO3CPU: Ticking main, FullO3CPU.
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79000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 FetchSeq=1 CPSeq=1 flags=(IsInteger)
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82500: O3CPU: system.cpu: Removing committed instruction [tid:0] PC (0x400084=>0x400088).(0=>1) [sn:1]
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82500: O3CPU: system.cpu: Removing instruction, [tid:0] [sn:1] PC (0x400084=>0x400088).(0=>1)
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82500: O3CPU: system.cpu: Scheduling next tick!
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83000: O3CPU: system.cpu:
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....
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which is the `movz` after the checkpoint. The final `m5exit` does not appear due to DerivO3CPU logging insanity.
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Bibliography:
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* https://stackoverflow.com/questions/49011096/how-to-switch-cpu-models-in-gem5-after-restoring-a-checkpoint-and-then-observe-t
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===== gem5 fast forward
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Besides switching CPUs after a checkpoint restore, fs.py also has the `--fast-forward` option to automatically run the script from the start on a less detailed CPU, and switch to a more detailed CPU at a given tick.
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This is generally useless compared to checkpoint restoring because:
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* checkpoint restore allows to run multiple contents after the restore, and restoring to multiple different system states, which you almost always want to do
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* we generally don't know the exact tick at which the region of interest will start, especially as the binaries change. It is much easier to just instrument the content with a checkoint <<m5ops,m5op>>
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But let's give it a try anyways with link:userland/freestanding/gem5_checkpoint_restore.S[] which was mentioned at <<gem5-checkpoint-userland-minimal-example>>
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....
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./run \
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--arch aarch64 \
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--emulator gem5 \
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--static \
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--trace ExecAll,FmtFlag,O3CPU,SimpleCPU \
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--userland userland/freestanding/gem5_checkpoint_restore.S \
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-- \
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--caches
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--cpu-type DerivO3CPU \
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--fast-forward 1000 \
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;
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cat "$(./getvar --arch aarch64 --emulator gem5 trace_txt_file)"
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....
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At gem5 2235168b72537535d74c645a70a85479801e0651 we see something like:
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....
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0: O3CPU: system.switch_cpus: Creating O3CPU object.
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0: O3CPU: system.switch_cpus: Workload[0] process is 0 0: SimpleCPU: system.cpu: ActivateContext 0
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x40 WriteReq
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...
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1f92 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e40 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e30 WriteReq
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0: SimpleCPU: system.cpu: Tick
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0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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500: SimpleCPU: system.cpu: Tick
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500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 : movz x1, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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1000: SimpleCPU: system.cpu: Tick
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1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 : m5checkpoint : IntAlu : flags=(IsInteger|IsNonSpeculative|IsUnverifiable)
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1000: O3CPU: system.switch_cpus: [tid:0] Calling activate thread.
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1000: O3CPU: system.switch_cpus: [tid:0] Adding to active threads list
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1500: O3CPU: system.switch_cpus:
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FullO3CPU: Ticking main, FullO3CPU.
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1500: O3CPU: system.switch_cpus: Scheduling next tick!
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2000: O3CPU: system.switch_cpus:
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FullO3CPU: Ticking main, FullO3CPU.
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2000: O3CPU: system.switch_cpus: Scheduling next tick!
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2500: O3CPU: system.switch_cpus:
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...
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FullO3CPU: Ticking main, FullO3CPU.
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44500: ExecEnable: system.switch_cpus: A0 T0 : @asm_main_after_prologue+12 : movz x0, #0, #0 : IntAlu : D=0x00000000000
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48000: O3CPU: system.switch_cpus: Removing committed instruction [tid:0] PC (0x400084=>0x400088).(0=>1) [sn:1]
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48000: O3CPU: system.switch_cpus: Removing instruction, [tid:0] [sn:1] PC (0x400084=>0x400088).(0=>1)
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48000: O3CPU: system.switch_cpus: Scheduling next tick!
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48500: O3CPU: system.switch_cpus:
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...
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....
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We can also compare that to the same log but without `--fast-forward` and other CPU switch options:
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....
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e40 WriteReq
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0: SimpleCPU: system.cpu.dcache_port: received snoop pkt for addr:0x1e30 WriteReq
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0: SimpleCPU: system.cpu: Tick
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0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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500: SimpleCPU: system.cpu: Tick
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500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 : movz x1, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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1000: SimpleCPU: system.cpu: Tick
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1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 : m5checkpoint : IntAlu : flags=(IsInteger|IsNonSpeculative|IsUnverifiable)
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1000: SimpleCPU: system.cpu: Resume
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1500: SimpleCPU: system.cpu: Tick
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1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
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2000: SimpleCPU: system.cpu: Tick
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2000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+16 : m5exit : No_OpClass : flags=(IsInteger|IsNonSpeculative)
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....
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Therefore, it is clear that what we wanted happen:
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* up until the tick 1000, `SimpleCPU` was ticking
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* after tick 1000, cpu `O3CPU` started ticking
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Bibliography:
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* https://cs.stackexchange.com/questions/69511/what-does-fast-forwarding-mean-in-the-context-of-cpu-simulation
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=== Pass extra options to gem5
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Remember that in the gem5 command line, we can either pass options to the script being run as in:
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