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x86 asm: address modes, LKMC_ASSET_EQ_32 and intel manuals
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Ciro Santilli 六四事件 法轮功
180
README.adoc
180
README.adoc
@@ -11737,34 +11737,34 @@ Like other userland programs, these programs can be run as explained at: <<userl
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As a quick reminder, the fastest setups to get started are:
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* <<userland-setup-getting-started-natively>> if your host can run the examples, e.g. x86 example on an x86 host
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* <<userland-setup-getting-started-natively>> if your host can run the examples, e.g. x86 example on an x86 host:
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* <<userland-setup-getting-started-with-prebuilt-toolchain-and-qemu-user-mode>> otherwise
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However, as usual, it is saner to build your toolchain as explained at: <<qemu-user-mode-getting-started>>.
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The first examples that you want to run for each arch are:
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The first examples you should look into are:
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* how to move data between registers and memory
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* how to add two numbers!
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These examples are located at:
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* x86
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* add
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** link:userland/arch/x86_64/add.S[]
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** link:userland/arch/x86_64/mov.S[]
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* arm
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** <<arm-mov-instruction>>
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** link:userland/arch/arm/add.S[]
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** link:userland/arch/aarch64/add.S[]
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* mov between register and memory
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** link:userland/arch/x86_64/mov.S[]
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** <<arm-mov-instruction>>
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** <<arm-load-and-store-instructions>>
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* addressing modes
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** <<x86-addressing-modes>>
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** <<arm-addressing-modes>>
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* registers: <<assembly-registers>>
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These examples use the venerable ADD instruction to:
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The add examples in particular:
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* introduce the basics of how a given assembly works: how many inputs / outputs, who is input and output, can it use memory or just registers, etc.
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+
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It is then a big copy paste for most other data instructions.
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* verify that the venerable `add` instruction and our assertions are working
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Then, modify that program to make the assertion fail:
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Now try to modify modify the x86_64 add program to see the assertion fail:
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....
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LKMC_ASSERT_EQ(%rax, $4)
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@@ -11969,6 +11969,47 @@ Examples under `arch/<arch>/c/` directories show to how use inline assembly from
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** link:userland/arch/aarch64/inline_asm/inc.c[]
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** link:userland/arch/aarch64/inline_asm/multiline.cpp[]
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==== GCC inline assembly register variables
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Used notably in some of the <<linux-system-calls>> setups:
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* link:userland/arch/arm/inline_asm/reg_var.c[]
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* link:userland/arch/aarch64/inline_asm/reg_var.c[]
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* link:userland/arch/aarch64/inline_asm/reg_var_float.c[]
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In x86, makes it possible to access variables not exposed with the one letter register constraints.
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In arm, it is the only way to achieve this effect: https://stackoverflow.com/questions/10831792/how-to-use-specific-register-in-arm-inline-assembler
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This feature notably useful for making system calls from C, see: <<linux-system-calls>>.
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Documentation: https://gcc.gnu.org/onlinedocs/gcc-4.4.2/gcc/Explicit-Reg-Vars.html
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==== GCC inline assembly scratch registers
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How to use temporary registers in inline assembly:
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* x86_64
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** link:userland/arch/x86_64/inline_asm/scratch.c[]
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** link:userland/arch/x86_64/inline_asm/scratch_hardcode.c[]
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Bibliography: https://stackoverflow.com/questions/6682733/gcc-prohibit-use-of-some-registers/54963829#54963829
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==== GCC inline assembly early-clobbers
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An example of using the `&` early-clobber modifier: link:userland/arch/aarch64/earlyclobber.c
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More details at: https://stackoverflow.com/questions/15819794/when-to-use-earlyclobber-constraint-in-extended-gcc-inline-assembly/54853663#54853663
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The assertion may fail without it. It actually does fail in GCC 8.2.0.
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==== GCC inline assembly floating point ARM
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Not documented as of GCC 8.2, but possible: https://stackoverflow.com/questions/53960240/armv8-floating-point-output-inline-assembly
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* link:userland/arch/arm/inline_asm/inc_float.c[]
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* link:userland/arch/aarch64/inline_asm/inc_float.c[]
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==== GCC intrinsics
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Pre-existing C wrappers using inline assembly, this is what production programs should use instead of inline assembly for SIMD:
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@@ -12034,47 +12075,6 @@ Bibliography:
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* https://www.cs.virginia.edu/~cr4bd/3330/S2018/simdref.html
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* https://software.intel.com/en-us/articles/how-to-use-intrinsics
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==== GCC inline assembly register variables
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Used notably in some of the <<linux-system-calls>> setups:
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* link:userland/arch/arm/inline_asm/reg_var.c[]
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* link:userland/arch/aarch64/inline_asm/reg_var.c[]
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* link:userland/arch/aarch64/inline_asm/reg_var_float.c[]
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In x86, makes it possible to access variables not exposed with the one letter register constraints.
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In arm, it is the only way to achieve this effect: https://stackoverflow.com/questions/10831792/how-to-use-specific-register-in-arm-inline-assembler
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This feature notably useful for making system calls from C, see: <<linux-system-calls>>.
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Documentation: https://gcc.gnu.org/onlinedocs/gcc-4.4.2/gcc/Explicit-Reg-Vars.html
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==== GCC inline assembly scratch registers
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How to use temporary registers in inline assembly:
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* x86_64
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** link:userland/arch/x86_64/inline_asm/scratch.c[]
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** link:userland/arch/x86_64/inline_asm/scratch_hardcode.c[]
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Bibliography: https://stackoverflow.com/questions/6682733/gcc-prohibit-use-of-some-registers/54963829#54963829
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==== GCC inline assembly early-clobbers
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An example of using the `&` early-clobber modifier: link:userland/arch/aarch64/earlyclobber.c
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More details at: https://stackoverflow.com/questions/15819794/when-to-use-earlyclobber-constraint-in-extended-gcc-inline-assembly/54853663#54853663
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The assertion may fail without it. It actually does fail in GCC 8.2.0.
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==== GCC inline assembly floating point ARM
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Not documented as of GCC 8.2, but possible: https://stackoverflow.com/questions/53960240/armv8-floating-point-output-inline-assembly
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* link:userland/arch/arm/inline_asm/inc_float.c[]
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* link:userland/arch/aarch64/inline_asm/inc_float.c[]
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=== Linux system calls
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The following <<userland-setup>> programs illustrate how to make system calls:
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@@ -12285,6 +12285,41 @@ Bibliography: https://stackoverflow.com/questions/27147043/n-suffix-to-branch-in
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Arch agnostic infrastructure getting started at: <<userland-assembly>>.
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=== x86 addressing modes
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Example: link:userland/arch/x86_64/address_modes.S[]
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Several x86 instructions can calculate addresses of a complex form:
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....
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s:a(b, c, d)
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....
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which expands to:
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....
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a + b + c * d
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....
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Where the instruction encoding allows for:
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* `a`: any 8 or 32-bit general purpose register
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* `b`: any 32-bit general purpose register except ESP
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* `c`: 1, 2, 4 or 8 (encoded in 2 SIB bits)
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* `d`: immediate constant
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* `s`: a segment register. Cannot be tested simply from userland, so we won't talk about them here. See: https://github.com/cirosantilli/x86-bare-metal-examples/blob/6606a2647d44bc14e6fd695c0ea2b6b7a5f04ca3/segment_registers_real_mode.S
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The common compiler usage is:
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* `a`: base pointer
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* `b`: array offset
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* `c` and `d`: struct offset
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Bibliography:
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* <<intel-manual-1>> 3.7.5 "Specifying an Offset"
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* https://sourceware.org/binutils/docs-2.18/as/i386_002dMemory.html
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=== x86 SIMD
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History:
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@@ -12348,6 +12383,43 @@ TODO We didn't manage to find a working ARM analogue to <<x86-rdtsc-instruction>
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* https://stackoverflow.com/questions/31620375/arm-cortex-a7-returning-pmccntr-0-in-kernel-mode-and-illegal-instruction-in-u/31649809#31649809
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* https://blog.regehr.org/archives/794
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=== x86 assembly bibliography
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==== x86 official bibliography
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[[intel-manual]]
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===== Intel 64 and IA-32 Architectures Software Developer's Manuals
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We are using the May 2019 version unless otherwise noted.
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There are a few download forms at: https://software.intel.com/en-us/articles/intel-sdm
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The single PDF one is useless however because it does not have a unified ToC nor inter Volume links, so I just download the 4-part one.
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The Volumes are well split, so it is usually easy to guess where you should look into.
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Also I can't find older versions on the website easily, so I just web archive everything.
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[[intel-manual-1]]
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====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 1
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Userland basics: http://web.archive.org/web/20190606075544/https://software.intel.com/sites/default/files/managed/a4/60/253665-sdm-vol-1.pdf
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[[intel-manual-2]]
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====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 2
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Instruction list: http://web.archive.org/web/20190606075330/https://software.intel.com/sites/default/files/managed/a4/60/325383-sdm-vol-2abcd.pdf
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[[intel-manual-3]]
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====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 2
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Kernel land: http://web.archive.org/web/20190606075534/https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf
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[[intel-manual-4]]
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====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 2
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Model specific extensions: http://web.archive.org/web/20190606075325/https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf
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== ARM userland assembly
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Arch general getting started at: <<userland-assembly>>.
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@@ -12,6 +12,15 @@
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call lkmc_assert_eq_64; \
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;
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#define LKMC_ASSERT_EQ_32(general1, general2) \
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mov general2, %edi; \
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push %rdi; \
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mov general1, %edi; \
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pop %rsi; \
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mov $__LINE__, %edx; \
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call lkmc_assert_eq_32; \
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;
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#define LKMC_ASSERT_FAIL \
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mov $__LINE__, %edi; \
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call lkmc_assert_fail; \
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95
userland/arch/x86_64/address_modes.S
Normal file
95
userland/arch/x86_64/address_modes.S
Normal file
@@ -0,0 +1,95 @@
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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-addressing-modes */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* First we play around with lea which is easier to assert. */
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/* Full form with immediates:
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*
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* rbx + rcx * 2 + 4 =
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* 3 + 4 * 2 + 4 =
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* 3 + 8 + 4 =
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* 3 + 8 + 4 =
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* 15
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*/
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mov $0, %rax
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mov $3, %rbx
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mov $4, %rcx
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/* GAS 2.24 Warning: segment override on `lea' is ineffectual. */
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/*lea %ds:4(%rbx, %rcx, 2), %rax*/
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lea 4(%rbx, %rcx, 2), %rax
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LKMC_ASSERT_EQ(%rax, $15)
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/* Omit the mulitplicator d.
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* a(b,c) == a(b,c,1)
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*/
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mov $0, %rax
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mov $3, %rbx
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mov $4, %rcx
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lea 2(%rbx, %rcx), %rax
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LKMC_ASSERT_EQ(%rax, $9)
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/* Omit c and d. */
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mov $0, %rax
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mov $1, %rbx
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lea 2(%rbx), %rax
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LKMC_ASSERT_EQ(%rax, $3)
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/* Register only address. We can omit commas. */
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mov $0, %rax
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mov $1, %rbx
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lea (%rbx), %rax
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LKMC_ASSERT_EQ(%rax, $1)
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/* TODO What is this syntax for? Compare to the next example. */
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mov $0, %rax
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lea 2(,1), %rax
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LKMC_ASSERT_EQ(%rax, $2)
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mov $0, %rax
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lea 2, %rax
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LKMC_ASSERT_EQ(%rax, $2)
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/* TODO What is this syntax for? Compare to the previous example. */
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mov $0, %rax
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lea (2), %rax
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LKMC_ASSERT_EQ(%rax, $2)
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mov $0, %rax
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mov $3, %rbx
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lea 2(,%rbx,4), %rax
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LKMC_ASSERT_EQ(%rax, $14)
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/* Expressions like (1 + 1) or more commonly (label + 1)
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* can be used like anywhere else: the assembler / linker resolve
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* them for us.
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*/
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mov $1, %rax
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lea (1 + 1)(%rax), %rax
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LKMC_ASSERT_EQ(%rax, $3)
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/* Now some examples with the label and actual memory movs just for concreteness. */
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.data
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myint: .long 0x12345678
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.text
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/* Pointer dereference: To get the actual address instead of the data, use `$`: */
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mov $myint, %rbx
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mov (%rbx), %eax
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LKMC_ASSERT_EQ_32(%eax, myint)
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/* Regular memory IO is just a subcase of the full addressing mode syntax! */
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mov $0, %rax
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movl $0x9ABCDEF0, myint
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mov myint, %rax
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LKMC_ASSERT_EQ_32(%eax, $0x9ABCDEF0)
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/* Other instructions like add can also use the addressing. */
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movl $1, myint
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mov $myint, %rbx
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addl $2, (%rbx)
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LKMC_ASSERT_EQ_32(myint, $3)
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LKMC_EPILOGUE
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