aarch64: fix ASSERT_EQ_REG tests on gem5

Was doing an 8-byte aligned store, which gem5 dislikes.

But the ARMARM says bad things may happen there, notably a signal:
"D1.8.2 SP alignment checking" so gem5 is not really too wrong,
QEMU just happens to work by chance.

userland/arch/aarch64/common_arch.h

@@ -16,9 +16,9 @@
 ;
 
 #define ASSERT_EQ_REG(reg1, reg2) \
-    str reg2, [sp, -8]!; \
+    str reg2, [sp, -16]!; \
     mov x0, reg1; \
-    ldr x1, [sp], 8; \
+    ldr x1, [sp], 16; \
     ASSERT_EQ_DO(64); \
 ;