arm asm el: document virtualization failure after FP enable patch

README.adoc

@@ -13443,6 +13443,22 @@ CurrentEL.EL 0x2
 CurrentEL.EL 0x3
 ....
 
+TODO: the call:
+
+....
+./run --arch arm --baremetal baremetal/arch/arm/dump_regs.c --emulator gem5 -- --param 'system.have_virtualization = True'
+....
+
+started failing with an exception since https://github.com/cirosantilli/linux-kernel-module-cheat/commit/add6eedb76636b8f443b815c6b2dd160afdb7ff4 at the instruction:
+
+....
+vmsr fpexc, r0
+....
+
+in link:baremetal/lib/arm.S[]. That patch however enables SIMD in baremetal, which I feel is more important.
+
+According to <<armarm7>>, access to that register is controlled by other registers `NSACR.{CP11, CP10}` and `HCPTR` so those must be turned off, but I'm lazy to investigate now, even just trying to dump those registers in link:baremetal/arch/arm/dump_regs.c[] also leads to exceptions...
+
 ==== svc
 
 This is the most basic example of exception handling we have.

baremetal/arch/arm/dump_regs.c

@@ -8,10 +8,19 @@ int main(void) {
     /* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-exception-levels */
     printf("CPSR.M 0x%" PRIX32 "\n", cpsr & 0xF);
 
-    /* TODO this is blowing up an exception, how to I read from it? */
-    /*uint32_t mvfr1;*/
-    /*__asm__ ("vmrs %0, mvfr1" : "=r" (mvfr1) : :);*/
-    /*printf("MVFR1 0x%" PRIX32 "\n", mvfr1);*/
+#if 0
+    /* TODO blows up exception in EL, but works with -machine secure=on. */
+    uint32_t nsacr;
+    __asm__ ("mrc p15, 0, %0, c1, c1, 2" : "=r" (nsacr) : :);
+    printf("NSACR 0x%" PRIX32 "\n", nsacr);
+#endif
+
+#if 0
+    /* TODO blows up exception. */
+    uint32_t mvfr1;
+    __asm__ ("vmrs %0, mvfr1" : "=r" (mvfr1) : :);
+    printf("MVFR1 0x%" PRIX32 "\n", mvfr1);
+#endif
 
     return 0;
 }