mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-23 02:05:57 +01:00
319 lines
13 KiB
C
319 lines
13 KiB
C
#ifndef LKMC_GICV3_H
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#define LKMC_GICV3_H
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#include <lkmc/aarch64.h>
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#include <lkmc/board.h>
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typedef int32_t irq_no;
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#define GIC_GICD_BASE (GIC_BASE)
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#define GIC_GICC_BASE (GIC_BASE + 0x10000)
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#define GIC_GICD_INT_PER_REG (32)
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#define GIC_GICD_IPRIORITY_PER_REG (4)
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#define GIC_GICD_IPRIORITY_SIZE_PER_REG (8)
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#define GIC_GICD_ITARGETSR_CORE0_TARGET_BMAP (0x01010101)
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#define GIC_GICD_ITARGETSR_PER_REG (4)
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#define GIC_GICD_ITARGETSR_SIZE_PER_REG (8)
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#define GIC_GICD_ICFGR_PER_REG (16)
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#define GIC_GICD_ICFGR_SIZE_PER_REG (2)
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#define GIC_GICD_ICENABLER_PER_REG (32)
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#define GIC_GICD_ISENABLER_PER_REG (32)
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#define GIC_GICD_ICPENDR_PER_REG (32)
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#define GIC_GICD_ISPENDR_PER_REG (32)
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/* 8.12 The GIC CPU interface register map */
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#define GIC_GICC_CTLR (GIC_GICC_BASE + 0x000) /* CPU Interface Control Register */
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#define GIC_GICC_PMR (GIC_GICC_BASE + 0x004) /* Interrupt Priority Mask Register */
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#define GIC_GICC_BPR (GIC_GICC_BASE + 0x008) /* Binary Point Register */
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#define GIC_GICC_IAR (GIC_GICC_BASE + 0x00C) /* Interrupt Acknowledge Register */
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#define GIC_GICC_EOIR (GIC_GICC_BASE + 0x010) /* End of Interrupt Register */
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#define GIC_GICC_RPR (GIC_GICC_BASE + 0x014) /* Running Priority Register */
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#define GIC_GICC_HPIR (GIC_GICC_BASE + 0x018) /* Highest Pending Interrupt Register */
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#define GIC_GICC_ABPR (GIC_GICC_BASE + 0x01C) /* Aliased Binary Point Register */
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#define GIC_GICC_IIDR (GIC_GICC_BASE + 0x0FC) /* CPU Interface Identification Register */
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/* 8.13.7 GICC_CTLR, CPU Interface Control Register */
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#define GICC_CTLR_ENABLE (0x1) /* Enable GICC */
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#define GICC_CTLR_DISABLE (0x0) /* Disable GICC */
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/* 8.13.14 GICC_PMR, CPU Interface Priority Mask Register */
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#define GICC_PMR_PRIO_MIN (0xff) /* The lowest level mask */
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#define GICC_PMR_PRIO_HIGH (0x0) /* The highest level mask */
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/* 8.13.6 GICC_BPR, CPU Interface Binary Point Register */
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/* In systems that support only one Security state, when GICC_CTLR.CBPR == 0,
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this register determines only Group 0 interrupt preemption. */
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#define GICC_BPR_NO_GROUP (0x0) /* handle all interrupts */
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/* 8.13.11 GICC_IAR, CPU Interface Interrupt Acknowledge Register */
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#define GICC_IAR_INTR_IDMASK (0x3ff) /* 0-9 bits means Interrupt ID */
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#define GICC_IAR_SPURIOUS_INTR (0x3ff) /* 1023 means spurious interrupt */
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/* 8.8 The GIC Distributor register map */
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#define GIC_GICD_CTLR (GIC_GICD_BASE + 0x000) /* Distributor Control Register */
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#define GIC_GICD_TYPER (GIC_GICD_BASE + 0x004) /* Interrupt Controller Type Register */
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#define GIC_GICD_IIDR (GIC_GICD_BASE + 0x008) /* Distributor Implementer Identification Register */
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#define GIC_GICD_IGROUPR(n) (GIC_GICD_BASE + 0x080 + ( (n) * 4 ) ) /* Interrupt Group Registers */
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#define GIC_GICD_ISENABLER(n) (GIC_GICD_BASE + 0x100 + ( (n) * 4 ) ) /* Interrupt Set-Enable Registers */
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#define GIC_GICD_ICENABLER(n) (GIC_GICD_BASE + 0x180 + ( (n) * 4 ) ) /* Interrupt Clear-Enable Registers */
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#define GIC_GICD_ISPENDR(n) (GIC_GICD_BASE + 0x200 + ( (n) * 4 ) ) /* Interrupt Set-Pending Registers */
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#define GIC_GICD_ICPENDR(n) (GIC_GICD_BASE + 0x280 + ( (n) * 4 ) ) /* Interrupt Clear-Pending Registers */
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#define GIC_GICD_ISACTIVER(n) (GIC_GICD_BASE + 0x300 + ( (n) * 4 ) ) /* Interrupt Set-Active Registers */
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#define GIC_GICD_ICACTIVER(n) (GIC_GICD_BASE + 0x380 + ( (n) * 4 ) ) /* Interrupt Clear-Active Registers */
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#define GIC_GICD_IPRIORITYR(n) (GIC_GICD_BASE + 0x400 + ( (n) * 4 ) ) /* Interrupt Priority Registers */
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#define GIC_GICD_ITARGETSR(n) (GIC_GICD_BASE + 0x800 + ( (n) * 4 ) ) /* Interrupt Processor Targets Registers */
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#define GIC_GICD_ICFGR(n) (GIC_GICD_BASE + 0xc00 + ( (n) * 4 ) ) /* Interrupt Configuration Registers */
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#define GIC_GICD_NSCAR(n) (GIC_GICD_BASE + 0xe00 + ( (n) * 4 ) ) /* Non-secure Access Control Registers */
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#define GIC_GICD_SGIR (GIC_GICD_BASE + 0xf00 ) /* Software Generated Interrupt Register */
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#define GIC_GICD_CPENDSGIR(n) (GIC_GICD_BASE + 0xf10 + ( (n) * 4 ) ) /* SGI Clear-Pending Registers */
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#define GIC_GICD_SPENDSGIR(n) (GIC_GICD_BASE + 0xf20 + ( (n) * 4 ) ) /* SGI Set-Pending Registers */
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/* 8.9.4 GICD_CTLR, Distributor Control Register */
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#define GIC_GICD_CTLR_ENABLE (0x1) /* Enable GICD */
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#define GIC_GICD_CTLR_DISABLE (0x0) /* Disable GICD */
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/* 8.9.7 GICD_ICFGR<n>, Interrupt Configuration Registers */
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#define GIC_GICD_ICFGR_LEVEL (0x0) /* level-sensitive */
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#define GIC_GICD_ICFGR_EDGE (0x2) /* edge-triggered */
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/* Register access macros for GICC */
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#define REG_GIC_GICC_CTLR ((volatile uint32_t *)(uintptr_t)GIC_GICC_CTLR)
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#define REG_GIC_GICC_PMR ((volatile uint32_t *)(uintptr_t)GIC_GICC_PMR)
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#define REG_GIC_GICC_BPR ((volatile uint32_t *)(uintptr_t)GIC_GICC_BPR)
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#define REG_GIC_GICC_IAR ((volatile uint32_t *)(uintptr_t)GIC_GICC_IAR)
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#define REG_GIC_GICC_EOIR ((volatile uint32_t *)(uintptr_t)GIC_GICC_EOIR)
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#define REG_GIC_GICC_RPR ((volatile uint32_t *)(uintptr_t)GIC_GICC_RPR)
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#define REG_GIC_GICC_HPIR ((volatile uint32_t *)(uintptr_t)GIC_GICC_HPIR)
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#define REG_GIC_GICC_ABPR ((volatile uint32_t *)(uintptr_t)GIC_GICC_ABPR)
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#define REG_GIC_GICC_IIDR ((volatile uint32_t *)(uintptr_t)GIC_GICC_IIDR)
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/* Register access macros for GICD */
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#define REG_GIC_GICD_CTLR ((volatile uint32_t *)(uintptr_t)GIC_GICD_CTLR)
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#define REG_GIC_GICD_TYPE ((volatile uint32_t *)(uintptr_t)GIC_GICD_TYPE)
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#define REG_GIC_GICD_IIDR ((volatile uint32_t *)(uintptr_t)GIC_GICD_IIDR)
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#define REG_GIC_GICD_IGROUPR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_IGROUPR(n))
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#define REG_GIC_GICD_ISENABLER(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ISENABLER(n))
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#define REG_GIC_GICD_ICENABLER(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ICENABLER(n))
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#define REG_GIC_GICD_ISPENDR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ISPENDR(n))
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#define REG_GIC_GICD_ICPENDR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ICPENDR(n))
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#define REG_GIC_GICD_ISACTIVER(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ISACTIVER(n))
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#define REG_GIC_GICD_ICACTIVER(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ICACTIVER(n))
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#define REG_GIC_GICD_IPRIORITYR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_IPRIORITYR(n))
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#define REG_GIC_GICD_ITARGETSR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ITARGETSR(n))
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#define REG_GIC_GICD_ICFGR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_ICFGR(n))
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#define REG_GIC_GICD_NSCAR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_NSCAR(n))
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#define REG_GIC_GICD_SGIR ((volatile uint32_t *)(uintptr_t)GIC_GICD_SGIR)
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#define REG_GIC_GICD_CPENDSGIR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_CPENDSGIR(n))
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#define REG_GIC_GICD_SPENDSGIR(n) ((volatile uint32_t *)(uintptr_t)GIC_GICD_SPENDSGIR(n))
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void gic_v3_initialize(void);
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void gic_v3_eoi(irq_no irq);
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int gic_v3_find_pending_irq(
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LkmcVectorExceptionFrame *exc __attribute__((unused)),
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irq_no *irqp
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);
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void gicd_disable_int(irq_no irq);
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void gicd_enable_int(irq_no irq);
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void gicd_clear_pending(irq_no irq);
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/* Initialize GIC Controller */
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static void init_gicc(void) {
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uint32_t pending_irq;
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/* Disable CPU interface */
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*REG_GIC_GICC_CTLR = GICC_CTLR_DISABLE;
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/* Set the priority level as the lowest priority.
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* Note: Higher priority corresponds to a lower Priority field value in the GIC_PMR.
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* In addition to this, writing 255 to the GICC_PMR always sets it to the
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* largest supported priority field value.
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*/
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*REG_GIC_GICC_PMR = GICC_PMR_PRIO_MIN;
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/* Handle all of interrupts in a single group */
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*REG_GIC_GICC_BPR = GICC_BPR_NO_GROUP;
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/* Clear all of the active interrupts */
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for (
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pending_irq = (*REG_GIC_GICC_IAR & GICC_IAR_INTR_IDMASK);
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pending_irq != GICC_IAR_SPURIOUS_INTR;
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pending_irq = (*REG_GIC_GICC_IAR & GICC_IAR_INTR_IDMASK)
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)
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*REG_GIC_GICC_EOIR = *REG_GIC_GICC_IAR;
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/* Enable CPU interface */
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*REG_GIC_GICC_CTLR = GICC_CTLR_ENABLE;
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}
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static void init_gicd(void) {
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int32_t i, regs_nr;
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/* Diable distributor */
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*REG_GIC_GICD_CTLR = GIC_GICD_CTLR_DISABLE;
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/* Disable all IRQs */
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regs_nr = (GIC_INT_MAX + GIC_GICD_INT_PER_REG - 1) / GIC_GICD_INT_PER_REG;
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for (i = 0; regs_nr > i; ++i)
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*REG_GIC_GICD_ICENABLER(i) = ~((uint32_t)(0));
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/* Clear all pending IRQs */
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regs_nr = (GIC_INT_MAX + GIC_GICD_INT_PER_REG - 1) / GIC_GICD_INT_PER_REG;
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for (i = 0; regs_nr > i; ++i)
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*REG_GIC_GICD_ICPENDR(i) = ~((uint32_t)(0));
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/* Set all of interrupt priorities as the lowest priority */
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regs_nr = ( GIC_INT_MAX + GIC_GICD_IPRIORITY_PER_REG - 1) /
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GIC_GICD_IPRIORITY_PER_REG ;
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for (i = 0; regs_nr > i; i++)
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*REG_GIC_GICD_IPRIORITYR(i) = ~((uint32_t)(0));
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/* Set target of all of shared peripherals to processor 0 */
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for (i = GIC_INTNO_SPI0 / GIC_GICD_ITARGETSR_PER_REG;
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( (GIC_INT_MAX + (GIC_GICD_ITARGETSR_PER_REG - 1) ) /
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GIC_GICD_ITARGETSR_PER_REG ) > i; ++i)
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*REG_GIC_GICD_ITARGETSR(i) =
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(uint32_t)GIC_GICD_ITARGETSR_CORE0_TARGET_BMAP;
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/* Set trigger type for all peripheral interrupts level triggered */
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for (i = GIC_INTNO_PPI0 / GIC_GICD_ICFGR_PER_REG;
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(GIC_INT_MAX + (GIC_GICD_ICFGR_PER_REG - 1)) / GIC_GICD_ICFGR_PER_REG > i; ++i)
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*REG_GIC_GICD_ICFGR(i) = GIC_GICD_ICFGR_LEVEL;
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/* Enable distributor */
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*REG_GIC_GICD_CTLR = GIC_GICD_CTLR_ENABLE;
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}
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/* Disable IRQ
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* @param[in] irq IRQ number
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*/
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void gicd_disable_int(irq_no irq) {
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*REG_GIC_GICD_ICENABLER( (irq / GIC_GICD_ICENABLER_PER_REG) ) =
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1U << ( irq % GIC_GICD_ICENABLER_PER_REG );
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}
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/* Enable IRQ
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* @param[in] irq IRQ number
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*/
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void gicd_enable_int(irq_no irq) {
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*REG_GIC_GICD_ISENABLER( (irq / GIC_GICD_ISENABLER_PER_REG) ) =
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1U << ( irq % GIC_GICD_ISENABLER_PER_REG );
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}
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/* Clear a pending interrupt
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* @param[in] irq IRQ number
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*/
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void gicd_clear_pending(irq_no irq) {
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*REG_GIC_GICD_ICPENDR( (irq / GIC_GICD_ICPENDR_PER_REG) ) =
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1U << ( irq % GIC_GICD_ICPENDR_PER_REG );
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}
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/* Probe pending interrupt
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* @param[in] irq IRQ number
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*/
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static int gicd_probe_pending(irq_no irq) {
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int is_pending;
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is_pending = ( *REG_GIC_GICD_ISPENDR( (irq / GIC_GICD_ISPENDR_PER_REG) ) &
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( 1U << ( irq % GIC_GICD_ISPENDR_PER_REG ) ) );
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return ( is_pending != 0 );
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}
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/* Set an interrupt target processor
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* @param[in] irq IRQ number
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* @param[in] p Target processor mask
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* 0x1 processor 0
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* 0x2 processor 1
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* 0x4 processor 2
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* 0x8 processor 3
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*/
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static void gicd_set_target(irq_no irq, uint32_t p){
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uint32_t shift;
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uint32_t reg;
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shift = (irq % GIC_GICD_ITARGETSR_PER_REG) * GIC_GICD_ITARGETSR_SIZE_PER_REG;
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reg = *REG_GIC_GICD_ITARGETSR(irq / GIC_GICD_ITARGETSR_PER_REG);
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reg &= ~( ((uint32_t)(0xff)) << shift);
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reg |= (p << shift);
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*REG_GIC_GICD_ITARGETSR(irq / GIC_GICD_ITARGETSR_PER_REG) = reg;
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}
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/* Set an interrupt priority
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* @param[in] irq IRQ number
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* @param[in] prio Interrupt priority in Arm specific expression
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*/
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static void gicd_set_priority(irq_no irq, uint32_t prio){
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uint32_t shift;
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uint32_t reg;
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shift = (irq % GIC_GICD_IPRIORITY_PER_REG) * GIC_GICD_IPRIORITY_SIZE_PER_REG;
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reg = *REG_GIC_GICD_IPRIORITYR(irq / GIC_GICD_IPRIORITY_PER_REG);
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reg &= ~(((uint32_t)(0xff)) << shift);
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reg |= (prio << shift);
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*REG_GIC_GICD_IPRIORITYR(irq / GIC_GICD_IPRIORITY_PER_REG) = reg;
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}
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/* Configure IRQ
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* @param[in] irq IRQ number
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* @param[in] config Configuration value for GICD_ICFGR
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*/
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static void gicd_config(irq_no irq, unsigned int config) {
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uint32_t shift;
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uint32_t reg;
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shift = (irq % GIC_GICD_ICFGR_PER_REG) * GIC_GICD_ICFGR_SIZE_PER_REG; /* GICD_ICFGR has 16 fields, each field has 2bits. */
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reg = *REG_GIC_GICD_ICFGR( irq / GIC_GICD_ICFGR_PER_REG);
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reg &= ~( ( (uint32_t)(0x03) ) << shift ); /* Clear the field */
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reg |= ( ( (uint32_t)config ) << shift ); /* Set the value to the field correponding to irq */
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*REG_GIC_GICD_ICFGR( irq / GIC_GICD_ICFGR_PER_REG) = reg;
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}
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/* Send End of Interrupt to IRQ line for GIC
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* @param[in] ctrlr IRQ controller information
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* @param[in] irq IRQ number
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*/
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void gic_v3_eoi(irq_no irq) {
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gicd_clear_pending(irq);
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}
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/* Initialize GIC IRQ controller */
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/* RyanYao: 2018/07/20
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* I supppose the current access is security, because GICD_CTLR.DS is 0b0 and
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* we can access.
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*/
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void gic_v3_initialize(void) {
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init_gicd();
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init_gicc();
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gicd_config(TIMER_IRQ, GIC_GICD_ICFGR_EDGE);
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gicd_set_priority(TIMER_IRQ, 0 << GIC_PRI_SHIFT ); /* Set priority */
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gicd_set_target(TIMER_IRQ, 0x1); /* processor 0 */
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gicd_clear_pending(TIMER_IRQ);
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gicd_enable_int(TIMER_IRQ);
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}
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/* Find pending IRQ
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* @param[in] exc An exception frame
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* @param[in,out] irqp An IRQ number to be processed
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*/
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int gic_v3_find_pending_irq(
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LkmcVectorExceptionFrame *exc __attribute__((unused)),
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irq_no *irqp
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) {
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int rc;
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irq_no i;
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for( i = 0; GIC_INT_MAX > i; ++i) {
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if ( gicd_probe_pending(i) ) {
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rc = 1;
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*irqp = i;
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goto found;
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}
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}
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rc = 0;
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found:
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return rc;
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}
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#endif
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