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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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691 lines
40 KiB
HTML
691 lines
40 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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</head>
|
||
<body id="gem5-functional-vs-atomic-vs-timing-memory-requests" class="article">
|
||
<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect4">
|
||
<h5 id="gem5-functional-vs-atomic-vs-timing-memory-requests"><a class="anchor" href="#gem5-functional-vs-atomic-vs-timing-memory-requests"></a><a class="link" href="#gem5-functional-vs-atomic-vs-timing-memory-requests">24.21.1.1. gem5 functional vs atomic vs timing memory requests</a></h5>
|
||
<div class="paragraph">
|
||
<p>gem5 memory requests can be classified in the following broad categories:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>functional: get the value magically, do not update caches, see also: <a href="gem5-functional-requests.html">gem5 functional requests</a></p>
|
||
</li>
|
||
<li>
|
||
<p>atomic: get the value now without making a <a href="gem5-event-queue.html">separate event</a>, but do not update caches. Cannot work in <a href="gem5-ruby-build.html">Ruby</a> due to fundamental limitations, mentioned in passing at: <a href="https://gem5.atlassian.net/browse/GEM5-676" class="bare">https://gem5.atlassian.net/browse/GEM5-676</a></p>
|
||
</li>
|
||
<li>
|
||
<p>timing: get the value simulating delays and updating caches</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This trichotomy can be notably seen in the definition of the <a href="https://github.com/gem5/gem5/blob/9fc9c67b4242c03f165951775be5cd0812f2a705/src/mem/port.hh#L75">MasterPort class</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>class MasterPort : public Port, public AtomicRequestProtocol,
|
||
public TimingRequestProtocol, public FunctionalRequestProtocol</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and the base classes are defined under <code>src/mem/protocol/</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Then, by reading the rest of the class, we see that the send methods are all boring, and just forward to some polymorphic receiver that does the actual interesting activity:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> Tick
|
||
sendAtomicSnoop(PacketPtr pkt)
|
||
{
|
||
return AtomicResponseProtocol::sendSnoop(_masterPort, pkt);
|
||
}
|
||
|
||
Tick
|
||
AtomicResponseProtocol::sendSnoop(AtomicRequestProtocol *peer, PacketPtr pkt)
|
||
{
|
||
assert(pkt->isRequest());
|
||
return peer->recvAtomicSnoop(pkt);
|
||
}</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The receive methods are therefore the interesting ones, and must be overridden on derived classes if they ever expect to receive such requests:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> Tick
|
||
recvAtomicSnoop(PacketPtr pkt) override
|
||
{
|
||
panic("%s was not expecting an atomic snoop request\n", name());
|
||
return 0;
|
||
}
|
||
|
||
void
|
||
recvFunctionalSnoop(PacketPtr pkt) override
|
||
{
|
||
panic("%s was not expecting a functional snoop request\n", name());
|
||
}
|
||
|
||
void
|
||
recvTimingSnoopReq(PacketPtr pkt) override
|
||
{
|
||
panic("%s was not expecting a timing snoop request.\n", name());
|
||
}</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>One question that comes up now is: but why do CPUs need to care about <a href="cache-coherence.html">snoop requests</a>?</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And one big answer is: to be able to implement LLSC atomicity as mentioned at: <a href="arm-ldxr-and-stxr-instructions.html">ARM LDXR and STXR instructions</a>, since when other cores update memory, they could invalidate the lock of the current core.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Then, as you might expect, we can see that for example <code>AtomicSimpleCPU</code> does not override <code>recvTimingSnoopReq</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Now let see which requests are generated by ordinary <a href="arm-ldr-instruction.html">ARM LDR instruction</a>. We run:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>./run \
|
||
--arch aarch64 \
|
||
--debug-vm \
|
||
--emulator gem5 \
|
||
--gem5-build-type debug \
|
||
--useland userland/arch/aarch64/freestanding/linux/hello.S \</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and then break at the methods of the LDR class <code>LDRXL64_LIT</code>: <a href="gem5-execute-vs-initiateacc-vs-completeacc.html">gem5 <code>execute</code> vs <code>initiateAcc</code> vs <code>completeAcc</code></a>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Before starting, we of course guess that:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><code>AtomicSimpleCPU</code> will be making atomic accesses from <code>execute</code></p>
|
||
</li>
|
||
<li>
|
||
<p><code>TimingSimpleCPU</code> will be making timing accesses from <code>initiateAcc</code>, which must generate the event which leads to <code>completeAcc</code></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>so let’s confirm it.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>We break on <code>ArmISAInst::LDRXL64_LIT::execute</code> which is what <code>AtomicSimpleCPU</code> uses, and that leads as expected to:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>MasterPort::sendAtomic
|
||
AtomicSimpleCPU::sendPacket
|
||
AtomicSimpleCPU::readMem
|
||
SimpleExecContext::readMem
|
||
readMemAtomic<(ByteOrder)1, ExecContext, unsigned long>
|
||
readMemAtomicLE<ExecContext, unsigned long>
|
||
ArmISAInst::LDRXL64_LIT::execute
|
||
AtomicSimpleCPU::tick</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Notably, <code>AtomicSimpleCPU::readMem</code> immediately translates the address, creates a packet, sends the atomic request, and gets the response back without any events.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And now if we do the same with <code>--cpu-type TimingSimpleCPU</code> and break at <code>ArmISAInst::LDRXL64_LIT::initiateAcc</code>, and then add another break for the next event schedule <code>b EventManager::schedule</code> (which we imagine is the memory read) we reach:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>EventManager::schedule
|
||
DRAMCtrl::addToReadQueue
|
||
DRAMCtrl::recvTimingReq
|
||
DRAMCtrl::MemoryPort::recvTimingReq
|
||
TimingRequestProtocol::sendReq
|
||
MasterPort::sendTimingReq
|
||
CoherentXBar::recvTimingReq
|
||
CoherentXBar::CoherentXBarSlavePort::recvTimingReq
|
||
TimingRequestProtocol::sendReq
|
||
MasterPort::sendTimingReq
|
||
TimingSimpleCPU::handleReadPacket
|
||
TimingSimpleCPU::sendData
|
||
TimingSimpleCPU::finishTranslation
|
||
DataTranslation<TimingSimpleCPU*>::finish
|
||
ArmISA::TLB::translateComplete
|
||
ArmISA::TLB::translateTiming
|
||
ArmISA::TLB::translateTiming
|
||
TimingSimpleCPU::initiateMemRead
|
||
SimpleExecContext::initiateMemRead
|
||
initiateMemRead<ExecContext, unsigned long>
|
||
ArmISAInst::LDRXL64_LIT::initiateAcc
|
||
TimingSimpleCPU::completeIfetch
|
||
TimingSimpleCPU::IcachePort::ITickEvent::process
|
||
EventQueue::serviceOne</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>so as expected we have <code>TimingRequestProtocol::sendReq</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Remember however that timing requests are a bit more complicated due to <a href="arm-paging.html">paging</a>, since the page table walk can itself lead to further memory requests.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>In this particular instance, the address being read with <code>ldr x2, =len</code> <a href="arm-ldr-pseudo-instruction.html">ARM LDR pseudo-instruction</a> is likely placed just after the text section, and therefore the pagewalk is already in the TLB due to previous instruction fetches, and this is because the translation just finished immediately going through <code>TimingSimpleCPU::finishTranslation</code>, some key snippets are:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
|
||
Translation *translation, Mode mode, TLB::ArmTranslationType tranType,
|
||
bool callFromS2)
|
||
{
|
||
bool delay = false;
|
||
Fault fault;
|
||
if (FullSystem)
|
||
fault = translateFs(req, tc, mode, translation, delay, true, tranType);
|
||
else
|
||
fault = translateSe(req, tc, mode, translation, delay, true);
|
||
if (!delay)
|
||
translation->finish(fault, req, tc, mode);
|
||
else
|
||
translation->markDelayed();</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and then <code>translateSe</code> does not use <code>delay</code> at all, so we learn that in syscall emulation, <code>delay</code> is always <code>false</code> and things progress immediately there. And then further down <code>TimingSimpleCPU::finishTranslation</code> does some more fault checking:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>void
|
||
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
|
||
{
|
||
if (state->getFault() != NoFault) {
|
||
translationFault(state->getFault());
|
||
} else {
|
||
if (!state->isSplit) {
|
||
sendData(state->mainReq, state->data, state->res,
|
||
state->mode == BaseTLB::Read);</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Tested in gem5 b1623cb2087873f64197e503ab8894b5e4d4c7b4.</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="gem5-functional-requests.html">gem5 functional requests</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>↑ Up: <a href="gem5-port-system.html">gem5 port system</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-functional-requests.html">gem5 functional requests</a> →</p>
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