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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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836 lines
44 KiB
HTML
836 lines
44 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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|
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</head>
|
||
<body id="arm-svc-instruction" class="article">
|
||
<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect3">
|
||
<h4 id="arm-svc-instruction"><a class="anchor" href="#arm-svc-instruction"></a><a class="link" href="#arm-svc-instruction">33.10.2. ARM SVC instruction</a></h4>
|
||
<div class="paragraph">
|
||
<p>This is the most basic example of exception handling we have.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>We a handler for SVC, do an SVC, and observe that the handler got called and returned from C and assembly:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>./run --arch aarch64 --baremetal baremetal/arch/aarch64/svc.c
|
||
./run --arch aarch64 --baremetal baremetal/arch/aarch64/svc_asm.S</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Sources:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/baremetal/arch/aarch64/svc.c">baremetal/arch/aarch64/svc.c</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/baremetal/arch/aarch64/svc_asm.S">baremetal/arch/aarch64/svc_asm.S</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Sample output for the C one:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>DAIF 0x3C0
|
||
SPSEL 0x1
|
||
VBAR_EL1 0x40000800
|
||
after_svc 0x4000209c
|
||
lkmc_vector_trap_handler
|
||
exc_type 0x11
|
||
exc_type is LKMC_VECTOR_SYNC_SPX
|
||
ESR 0x5600ABCD
|
||
ESR.EC 0x15
|
||
ESR.EC.ISS.imm16 0xABCD
|
||
SP 0x4200C510
|
||
ELR 0x4000209C
|
||
SPSR 0x600003C5
|
||
x0 0x0
|
||
x1 0x1
|
||
x2 0x15
|
||
x3 0x15
|
||
x4 0x4000A178
|
||
x5 0xFFFFFFF6
|
||
x6 0x4200C390
|
||
x7 0x78
|
||
x8 0x1
|
||
x9 0x14
|
||
x10 0x0
|
||
x11 0x0
|
||
x12 0x0
|
||
x13 0x0
|
||
x14 0x0
|
||
x15 0x0
|
||
x16 0x0
|
||
x17 0x0
|
||
x18 0x0
|
||
x19 0x0
|
||
x20 0x0
|
||
x21 0x0
|
||
x22 0x0
|
||
x23 0x0
|
||
x24 0x0
|
||
x25 0x0
|
||
x26 0x0
|
||
x27 0x0
|
||
x28 0x0
|
||
x29 0x4200C510
|
||
x30 0x40002064</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The C code does an:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>svc 0xABCD</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and the value 0xABCD appears at the bottom of <a href="arm-esr-register.html">ARM ESR register</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>ESR 0x5600ABCD
|
||
ESR.EC 0x15
|
||
ESR.EC.ISS.imm16 0xABCD</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The other important register is the <a href="arm-elr-register.html">ARM ELR register</a>, which contains the return address after the exception.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>From the output, we can see that it matches the value as obtained by taking the address of a label placed just after the SVC:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>after_svc 0x4000209c
|
||
ELR 0x4000209C</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Both QEMU and gem5 are able to trace interrupts in addition to instructions, and it is instructive to enable both and have a look at the traces.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>With <a href="qemu-d-tracing.html">QEMU -d tracing</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>./run \
|
||
--arch aarch64 \
|
||
--baremetal baremetal/arch/aarch64/svc.c \
|
||
-- -d in_asm,int \
|
||
;</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>the output at 8f73910dd1fc1fa6dc6904ae406b7598cdcd96d7 contains:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>----------------
|
||
IN: main
|
||
0x40002098: d41579a1 svc #0xabcd
|
||
|
||
Taking exception 2 [SVC]
|
||
...from EL1 to EL1
|
||
...with ESR 0x15/0x5600abcd
|
||
...with ELR 0x4000209c
|
||
...to EL1 PC 0x40000a00 PSTATE 0x3c5
|
||
----------------
|
||
IN:
|
||
0x40000a00: 14000225 b #0x40001294
|
||
|
||
----------------
|
||
IN:
|
||
0x40001294: a9bf7bfd stp x29, x30, [sp, #-0x10]!
|
||
0x40001298: a9bf73fb stp x27, x28, [sp, #-0x10]!
|
||
0x4000129c: a9bf6bf9 stp x25, x26, [sp, #-0x10]!
|
||
0x400012a0: a9bf63f7 stp x23, x24, [sp, #-0x10]!
|
||
0x400012a4: a9bf5bf5 stp x21, x22, [sp, #-0x10]!
|
||
0x400012a8: a9bf53f3 stp x19, x20, [sp, #-0x10]!
|
||
0x400012ac: a9bf4bf1 stp x17, x18, [sp, #-0x10]!
|
||
0x400012b0: a9bf43ef stp x15, x16, [sp, #-0x10]!
|
||
0x400012b4: a9bf3bed stp x13, x14, [sp, #-0x10]!
|
||
0x400012b8: a9bf33eb stp x11, x12, [sp, #-0x10]!
|
||
0x400012bc: a9bf2be9 stp x9, x10, [sp, #-0x10]!
|
||
0x400012c0: a9bf23e7 stp x7, x8, [sp, #-0x10]!
|
||
0x400012c4: a9bf1be5 stp x5, x6, [sp, #-0x10]!
|
||
0x400012c8: a9bf13e3 stp x3, x4, [sp, #-0x10]!
|
||
0x400012cc: a9bf0be1 stp x1, x2, [sp, #-0x10]!
|
||
0x400012d0: d5384015 mrs x21, spsr_el1
|
||
0x400012d4: a9bf03f5 stp x21, x0, [sp, #-0x10]!
|
||
0x400012d8: d5384035 mrs x21, elr_el1
|
||
0x400012dc: a9bf57ff stp xzr, x21, [sp, #-0x10]!
|
||
0x400012e0: d2800235 movz x21, #0x11
|
||
0x400012e4: d5385216 mrs x22, esr_el1
|
||
0x400012e8: a9bf5bf5 stp x21, x22, [sp, #-0x10]!
|
||
0x400012ec: 910003f5 mov x21, sp
|
||
0x400012f0: 910482b5 add x21, x21, #0x120
|
||
0x400012f4: f9000bf5 str x21, [sp, #0x10]
|
||
0x400012f8: 910003e0 mov x0, sp
|
||
0x400012fc: 9400023f bl #0x40001bf8
|
||
|
||
----------------
|
||
IN: lkmc_vector_trap_handler
|
||
0x40001bf8: a9bd7bfd stp x29, x30, [sp, #-0x30]!</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And with <a href="gem5-tracing.html">gem5 tracing</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>./run \
|
||
--arch aarch64 \
|
||
--baremetal baremetal/arch/aarch64/svc_asm.S \
|
||
--trace ExecAll,Faults \
|
||
--trace-stdout \
|
||
;</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>the output contains:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 4000: system.cpu A0 T0 : @main+8 : svc #0x0 : IntAlu : flags=(IsSerializeAfter|IsNonSpeculative|IsSyscall)
|
||
4000: Supervisor Call: Invoking Fault (AArch64 target EL):Supervisor Call cpsr:0x3c5 PC:0x80000808 elr:0x8000080c newVec: 0x80001200
|
||
4500: system.cpu A0 T0 : @vector_table+512 : b <_curr_el_spx_sync> : IntAlu : flags=(IsControl|IsDirectControl|IsUncondControl)</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>So we see in both cases that the:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>SVC is done</p>
|
||
</li>
|
||
<li>
|
||
<p>an exception happens, and the PC jumps to address 0x40000a00. From our custom terminal prints further on, we see that this equals <code>VBAR_EL1 + 0x200</code>.</p>
|
||
<div class="paragraph">
|
||
<p>According to the format of the <a href="armv8-exception-vector-table-format.html">ARMv8 exception vector table format</a>, we see that the <code>+ 0x200</code> means that we are jumping in the Current EL with SPx.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This can also be deduced from the message <code>exc_type is LKMC_VECTOR_SYNC_SPX</code>: we just manually store a different integer for every exception vector type in our handler code to be able to tell what happened.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This is the one used because we are jumping <a href="arm-exception-levels.html">from EL1 to EL1</a>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>We set VBAR_EL1 to that address ourselves <a href="baremetal-bootloaders.html">in the bootloader</a>.</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>at 0x40000a00 a <code>b #0x40001294</code> is done and then at 0x40001294 boilerplate preparation is done for lkmc_vector_trap_handler starting with several STP instructions.</p>
|
||
<div class="paragraph">
|
||
<p>We have coded both of those in our vector table macro madness. As of LKMC 8f73910dd1fc1fa6dc6904ae406b7598cdcd96d7, both come from <a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/lkmc/aarch64.h">lkmc/aarch64.h</a>:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><code>b #0x40001294</code> comes from: <code>LKMC_VECTOR_ENTRY</code></p>
|
||
</li>
|
||
<li>
|
||
<p>the STP come from: <code>LKMC_VECTOR_BUILD_TRAPFRAME</code></p>
|
||
<div class="paragraph">
|
||
<p>We jump immediately from inside <code>LKMC_VECTOR_ENTRY</code> to <code>LKMC_VECTOR_BUILD_TRAPFRAME</code> because we can only use 0x80 bytes of instructions for each one before reaching the next handler, so we might as well get it over with by jumping into a memory region without those constraints.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO: why doesn’t QEMU show our nice symbol names? gem5 shows them fine, and <code>nm</code> says they are there!</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>0000000040000800 T lkmc_vector_table
|
||
0000000040001294 T lkmc_vector_build_trapframe_curr_el_spx_sync</pre>
|
||
</div>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The exception return happens at the end of <code>lkmc_vector_trap_handler</code>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>----------------
|
||
IN: lkmc_vector_trap_handler
|
||
0x40002000: d503201f nop
|
||
0x40002004: a8c37bfd ldp x29, x30, [sp], #0x30
|
||
0x40002008: d65f03c0 ret
|
||
|
||
----------------
|
||
IN:
|
||
0x40001300: 910043ff add sp, sp, #0x10
|
||
0x40001304: a8c15bf5 ldp x21, x22, [sp], #0x10
|
||
0x40001308: d5184036 msr elr_el1, x22
|
||
|
||
----------------
|
||
IN:
|
||
0x4000130c: a8c103f5 ldp x21, x0, [sp], #0x10
|
||
0x40001310: d5184015 msr spsr_el1, x21
|
||
|
||
----------------
|
||
IN:
|
||
0x40001314: a8c10be1 ldp x1, x2, [sp], #0x10
|
||
0x40001318: a8c113e3 ldp x3, x4, [sp], #0x10
|
||
0x4000131c: a8c11be5 ldp x5, x6, [sp], #0x10
|
||
0x40001320: a8c123e7 ldp x7, x8, [sp], #0x10
|
||
0x40001324: a8c12be9 ldp x9, x10, [sp], #0x10
|
||
0x40001328: a8c133eb ldp x11, x12, [sp], #0x10
|
||
0x4000132c: a8c13bed ldp x13, x14, [sp], #0x10
|
||
0x40001330: a8c143ef ldp x15, x16, [sp], #0x10
|
||
0x40001334: a8c14bf1 ldp x17, x18, [sp], #0x10
|
||
0x40001338: a8c153f3 ldp x19, x20, [sp], #0x10
|
||
0x4000133c: a8c15bf5 ldp x21, x22, [sp], #0x10
|
||
0x40001340: a8c163f7 ldp x23, x24, [sp], #0x10
|
||
0x40001344: a8c16bf9 ldp x25, x26, [sp], #0x10
|
||
0x40001348: a8c173fb ldp x27, x28, [sp], #0x10
|
||
0x4000134c: a8c17bfd ldp x29, x30, [sp], #0x10
|
||
0x40001350: d69f03e0 eret
|
||
|
||
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x4000209c
|
||
----------------
|
||
IN: main
|
||
0x4000209c: d0000040 adrp x0, #0x4000c000</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which does an <code>eret</code> and jumps back to 0x4000209c, which is 4 bytes and therefore one instruction after where SVC was taken at 0x40002098.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>On the terminal output, we observe the initial values of:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>DAIF: 0x3c0, i.e. 4 bits (6 to 9) set to 1, which means that exceptions are masked for each exception type: Synchronous, System error, IRQ and FIQ.</p>
|
||
<div class="paragraph">
|
||
<p>This reset value is defined by <a href="armarm8.html">ARMv8 architecture reference manual</a> C5.2.2 "DAIF, Interrupt Mask Bits".</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>SPSel: 0x1, which means: use SPx instead of SP0.</p>
|
||
<div class="paragraph">
|
||
<p>This reset value is defined by <a href="armarm8.html">ARMv8 architecture reference manual</a> C5.2.16 "SPSel, Stack Pointer Select".</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>VBAR_EL1: 0x0 holds the base address of the vector table</p>
|
||
<div class="paragraph">
|
||
<p>This reset value is defined UNKNOWN by <a href="armarm8.html">ARMv8 architecture reference manual</a> D10.2.116 "VBAR_EL1, Vector Base Address Register (EL1)", so we must set it to something ourselves to have greater portability.</p>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Bibliography:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="https://github.com/torvalds/linux/blob/v4.20/arch/arm64/kernel/entry.S#L430" class="bare">https://github.com/torvalds/linux/blob/v4.20/arch/arm64/kernel/entry.S#L430</a> this is where the kernel defines the vector table</p>
|
||
</li>
|
||
<li>
|
||
<p><a href="https://github.com/dwelch67/qemu_arm_samples/tree/07162ba087111e0df3f44fd857d1b4e82458a56d/swi01" class="bare">https://github.com/dwelch67/qemu_arm_samples/tree/07162ba087111e0df3f44fd857d1b4e82458a56d/swi01</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="https://github.com/NienfengYao/armv8-bare-metal/blob/572c6f95880e70aa92fe9fed4b8ad7697082a764/vector.S#L168" class="bare">https://github.com/NienfengYao/armv8-bare-metal/blob/572c6f95880e70aa92fe9fed4b8ad7697082a764/vector.S#L168</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="https://stackoverflow.com/questions/24162109/arm-assembly-code-and-svc-numbering/57064062#57064062" class="bare">https://stackoverflow.com/questions/24162109/arm-assembly-code-and-svc-numbering/57064062#57064062</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="https://stackoverflow.com/questions/44991264/armv8-exception-vectors-and-handling" class="bare">https://stackoverflow.com/questions/44991264/armv8-exception-vectors-and-handling</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="armv8-exception-vector-table-format.html">ARMv8 exception vector table format</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="arm-esr-register.html">ARM ESR register</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="arm-elr-register.html">ARM ELR register</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>← Previous: <a href="arm-sp0-vs-spx.html">ARM SP0 vs SPx</a> | ↑ Up: <a href="arm-baremetal.html">ARM baremetal</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="armv8-exception-vector-table-format.html">ARMv8 exception vector table format</a> →</p>
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