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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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b3874cc72b
To help with backtraces if we ever fix them due to the lkmc_asm_main_after_prologue debacle.
69 lines
2.0 KiB
ArmAsm
69 lines
2.0 KiB
ArmAsm
/* https://github.com/cirosantilli/linux-kernel-module-cheat#assembly-registers */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 13 general purpose registers. */
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mov r0, 0
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mov r1, 1
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mov r2, 2
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mov r3, 3
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mov r4, 4
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mov r5, 5
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mov r6, 6
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mov r7, 7
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mov r8, 8
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mov r9, 9
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mov r10, 10
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mov r11, 11
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mov r12, 12
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/* * r11: aliased to FP (frame pointer, debug stack trace usage only)
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* +
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* I think FP is only a convention with no instruction impact, but TODO:
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* not mentioned on AAPCS. aarch64 AAPCS mentions it though.
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* * r13: aliased to SP (stack pointer), what push / pop use
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* * r14: aliased to LR (link register), what bl writes the return address to
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* * r15: aliased to PC (program counter), contains the current instruction address
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*
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* In ARMv8, SP and PC have dedicated registers in addition to
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* the 32-general purpose ones. LR is still general purpose as before.
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*
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* Therefore, it is possible to use those registers in any place
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* other registers may be used.
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*
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* This is not possible in ARMv8 anymore.
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*
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* For example, we can load an address into PC, which is very similar to what B / BX does:
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* https://stackoverflow.com/questions/32304646/arm-assembly-branch-to-address-inside-register-or-memory/54145818#54145818
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*/
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ldr pc, =10f
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LKMC_ASSERT_FAIL
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10:
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/* Same with r15, which is the same as pc. */
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ldr r15, =10f
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LKMC_ASSERT_FAIL
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10:
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/* Another example with mov reading from pc. */
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mov r0, pc
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/* Why sub 8:
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* https://stackoverflow.com/questions/24091566/why-does-the-arm-pc-register-point-to-the-instruction-after-the-next-one-to-be-e
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*/
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sub r0, r0, 8
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/* pc-relative load also just work just like any other register. */
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ldr r0, [pc]
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b 1f
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.word 0x12345678
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1:
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LKMC_ASSERT_EQ(r0, =0x12345678)
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/* We can also use fp in GNU GAS assembly. */
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mov r11, 0
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mov fp, 1
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LKMC_ASSERT_EQ(r11, =1)
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LKMC_EPILOGUE
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