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linux-kernel-module-cheat/vi-cache-coherence-protocol.html
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2025-05-10 07:50:53 +01:00

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<meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. EVERYTHING is built from source. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
<title>Linux Kernel Module Cheat</title>
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</head>
<body id="vi-cache-coherence-protocol" class="article">
<div id="header">
<h1>Linux Kernel Module Cheat</h1>
</div>
<div id="content">
<div class="sect4">
<h5 id="vi-cache-coherence-protocol"><a class="anchor" href="#vi-cache-coherence-protocol"></a><a class="link" href="#vi-cache-coherence-protocol">37.6.1.3. VI cache coherence protocol</a></h5>
<div class="paragraph">
<p>Mentioned at:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><a href="http://courses.csail.mit.edu/6.888/spring13/lectures/L7-coherence.pdf" class="bare">http://courses.csail.mit.edu/6.888/spring13/lectures/L7-coherence.pdf</a></p>
</li>
<li>
<p><a href="http://csg.csail.mit.edu/6.823S16/lectures/L15.pdf" class="bare">http://csg.csail.mit.edu/6.823S16/lectures/L15.pdf</a></p>
</li>
</ul>
</div>
<div class="paragraph">
<p>This is the most trivial, but likely it is too bad and most sources don&#8217;t even mention it.</p>
</div>
<div class="paragraph">
<p>In what follows I make some stuff up with design choice comparisons, needs confirmation.</p>
</div>
<div class="paragraph">
<p>In this protocol, every cache only needs a single bit of state: validity.</p>
</div>
<div class="paragraph">
<p>At the start, everything is invalid.</p>
</div>
<div class="paragraph">
<p>Then, when you need to read and are invalid, you send a read on bus. If there is another valid cache in another CPU, it services the request. Otherwise, goes the request goes to memory. After read you become valid.</p>
</div>
<div class="paragraph">
<p>Read for valid generates no bus requests, which is good.</p>
</div>
<div class="paragraph">
<p>When you write, if you are invalid, you must first read to get the full cache line, like for any other protocol.</p>
</div>
<div class="paragraph">
<p>Then, there are two possible design choices, either:</p>
</div>
<div class="ulist">
<ul>
<li>
<p>that read is marked as exclusive, and all caches that had it, snoop it become invalid.</p>
<div class="paragraph">
<p>Upside: no need to send the new data to the bus.</p>
</div>
<div class="paragraph">
<p>Downside: more invalidations. But those are not too serious, because future invalid reads tend to just hit the remaining valid cache.</p>
</div>
</li>
<li>
<p>after the read and write, you send the data on the bus, and those that had it update and become valid.</p>
<div class="paragraph">
<p>Downside: much more data on bus, so likely this is not going to be the best choice.</p>
</div>
</li>
</ul>
</div>
<div class="paragraph">
<p>So we take the first option.</p>
</div>
<div class="paragraph">
<p>When you write and are valid, you don&#8217;t need to read. But you still have invalidate everyone else, because multiple reads can lead to multiple valid holders, otherwise other valid holders would keep reading old values.</p>
</div>
<div class="paragraph">
<p>We could either do this with an exclusive read, and ignore the return, or with a new Invalidate request that has no reply. This invalidation is called <code>BusUpgr</code> to match with Wikipedia.</p>
</div>
<div class="paragraph">
<p>Write also has two other possible design choices, either:</p>
</div>
<div class="ulist">
<ul>
<li>
<p>every write writes through to memory. This is likely never the best option.</p>
</li>
<li>
<p>when the cache is full, eviction leads to a write to memory.</p>
<div class="paragraph">
<p>If multiple valid holders may exist, then this may lead to multiple write through evictions of the same thing.</p>
</div>
</li>
</ul>
</div>
<div class="paragraph">
<p>So we take the second option.</p>
</div>
<div class="paragraph">
<p>With this we would have:</p>
</div>
<div class="ulist">
<ul>
<li>
<p>V</p>
<div class="ulist">
<ul>
<li>
<p>PrRd</p>
<div class="ulist">
<ul>
<li>
<p>V
<strong>*</strong></p>
</li>
</ul>
</div>
</li>
<li>
<p>PrWr</p>
<div class="ulist">
<ul>
<li>
<p>V</p>
</li>
<li>
<p>BusUpgr</p>
</li>
</ul>
</div>
</li>
<li>
<p>BusRd</p>
<div class="ulist">
<ul>
<li>
<p>V</p>
</li>
<li>
<p>BusData</p>
</li>
</ul>
</div>
</li>
<li>
<p>BusRdX</p>
<div class="ulist">
<ul>
<li>
<p>I</p>
</li>
<li>
<p>BusData</p>
</li>
</ul>
</div>
</li>
<li>
<p>BusUpgr</p>
<div class="ulist">
<ul>
<li>
<p>I
<strong>*</strong></p>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
<li>
<p>I</p>
<div class="ulist">
<ul>
<li>
<p>PrRd</p>
<div class="ulist">
<ul>
<li>
<p>V</p>
</li>
<li>
<p>BusRd</p>
</li>
</ul>
</div>
</li>
<li>
<p>PrWr</p>
<div class="ulist">
<ul>
<li>
<p>V</p>
</li>
<li>
<p>BusRdX</p>
</li>
</ul>
</div>
</li>
<li>
<p>BusRd</p>
<div class="ulist">
<ul>
<li>
<p>I
<strong>*</strong></p>
</li>
</ul>
</div>
</li>
<li>
<p>BusRdX</p>
<div class="ulist">
<ul>
<li>
<p>I
<strong>*</strong></p>
</li>
</ul>
</div>
</li>
<li>
<p>BusUpgr</p>
<div class="ulist">
<ul>
<li>
<p>I
<strong>*</strong></p>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
<div class="paragraph">
<p>Here Flush and BusData replies are omitted since those never lead to a change of state, nor to the sending of further messages.</p>
</div>
<div class="paragraph">
<p>TODO at:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><a href="http://courses.csail.mit.edu/6.888/spring13/lectures/L7-coherence.pdf" class="bare">http://courses.csail.mit.edu/6.888/spring13/lectures/L7-coherence.pdf</a></p>
</li>
<li>
<p><a href="http://csg.csail.mit.edu/6.823S16/lectures/L15.pdf" class="bare">http://csg.csail.mit.edu/6.823S16/lectures/L15.pdf</a></p>
</li>
</ul>
</div>
<div class="paragraph">
<p>why PrWr stays in invalid? Why do writes always go to memory? Why not wait until eviction?</p>
</div>
<div class="ulist">
<ul>
</ul>
</div>
</div>
<div class="paragraph nav-footer">
<p>← Previous: <a href="can-caches-snoop-data-from-other-caches.html">Can caches snoop data from other caches?</a> | ↑ Up: <a href="cache-coherence.html">Cache coherence</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="msi-cache-coherence-protocol.html">MSI cache coherence protocol</a> →</p>
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