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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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602 lines
37 KiB
HTML
602 lines
37 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. EVERYTHING is built from source. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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</head>
|
||
<body id="arm-instruction-encodings" class="article">
|
||
<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect3">
|
||
<h4 id="arm-instruction-encodings"><a class="anchor" href="#arm-instruction-encodings"></a><a class="link" href="#arm-instruction-encodings">30.1.3. ARM instruction encodings</a></h4>
|
||
<div class="paragraph">
|
||
<p>Understanding the basics of instruction encodings is fundamental to help you to remember what instructions do and why some things are possible or not, notably the <a href="arm-ldr-pseudo-instruction.html">ARM LDR pseudo-instruction</a> and the <a href="arm-adr-instruction.html">ADRP instruction</a>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>aarch32 has two "instruction sets", which to look just like encodings.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The encodings are:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>A32: every instruction is 4 bytes long. Can encode every instruction.</p>
|
||
</li>
|
||
<li>
|
||
<p>T32: most common instructions are 2 bytes long. Many others less common ones are 4 bytes long.</p>
|
||
<div class="paragraph">
|
||
<p>T stands for "Thumb", which is the original name for the technology, <a href="armarm8.html">ARMv8 architecture reference manual</a> A1.3.2 "The ARM instruction sets" says:</p>
|
||
</div>
|
||
<div class="quoteblock">
|
||
<blockquote>
|
||
<div class="paragraph">
|
||
<p>In previous documentation, these instruction sets were called the ARM and Thumb instruction sets</p>
|
||
</div>
|
||
</blockquote>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>See also: <a href="armarm8.html">ARMv8 architecture reference manual</a> F2.1.3 "Instruction encodings".</p>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Within each instruction set, there can be multiple encodings for a given function, and they are noted simply as:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>A1, A2, …​: A32 encodings</p>
|
||
</li>
|
||
<li>
|
||
<p>T1, T2, ..m: T32 encodings</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The state bit <code>PSTATE.T</code> determines if the processor is in thumb mode or not. <a href="armarm8.html">ARMv8 architecture reference manual</a> says that this bit it can only be read from <a href="arm-bx-instruction.html">ARM BX instruction</a></p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p><a href="https://stackoverflow.com/questions/22660025/how-can-i-tell-if-i-am-in-arm-mode-or-thumb-mode-in-gdb" class="bare">https://stackoverflow.com/questions/22660025/how-can-i-tell-if-i-am-in-arm-mode-or-thumb-mode-in-gdb</a></p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO: details: <a href="https://stackoverflow.com/questions/22660025/how-can-i-tell-if-i-am-in-arm-mode-or-thumb-mode-in-gdb" class="bare">https://stackoverflow.com/questions/22660025/how-can-i-tell-if-i-am-in-arm-mode-or-thumb-mode-in-gdb</a> says it is <code>0x20 & CPSR</code>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This RISC-y mostly fixed instruction length design likely makes processor design easier and allows for certain optimizations, at the cost of slightly more complex assembly, as you can’t encode 4 / 8 byte addresses in a single instruction. Totally worth it IMHO.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This design can be contrasted with x86, which has widely variable instruction length.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>We can swap between A32 and T32 with the BX and BLX instructions: <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0100a/armasm_cihfddaf.htm" class="bare">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0100a/armasm_cihfddaf.htm</a> puts it really nicely:</p>
|
||
</div>
|
||
<div class="quoteblock">
|
||
<blockquote>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>The BL and BLX instructions copy the address of the next instruction into lr (r14, the link register).</p>
|
||
</li>
|
||
<li>
|
||
<p>The BX and BLX instructions can change the processor state from ARM to Thumb, or from Thumb to ARM.</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>BLX label always changes the state.</p>
|
||
</li>
|
||
<li>
|
||
<p>BX Rm and BLX Rm derive the target state from bit[0] of Rm:</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state</p>
|
||
</li>
|
||
<li>
|
||
<p>if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The BXJ instruction changes the processor state to Jazelle.</p>
|
||
</div>
|
||
</blockquote>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Bibliography:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="https://stackoverflow.com/questions/28669905/what-is-the-difference-between-the-arm-thumb-and-thumb-2-instruction-encodings" class="bare">https://stackoverflow.com/questions/28669905/what-is-the-difference-between-the-arm-thumb-and-thumb-2-instruction-encodings</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="arm-thumb-encoding.html">ARM Thumb encoding</a></p>
|
||
</li>
|
||
<li>
|
||
<p><a href="arm-big-endian-mode.html">ARM big endian mode</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>← Previous: <a href="free-arm-implementations.html">Free ARM implementations</a> | ↑ Up: <a href="introduction-to-the-arm-architecture.html">Introduction to the ARM architecture</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="arm-thumb-encoding.html">ARM Thumb encoding</a> →</p>
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