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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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74 lines
2.0 KiB
ArmAsm
74 lines
2.0 KiB
ArmAsm
/* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-vadd-instruction
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* Adapted from: https://mindplusplus.wordpress.com/2013/06/27/arm-vfp-vector-programming-part-2-examples/ */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* Minimal single precision floating point example.
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* TODO: floating point representation constraints due to 4-byte instruction?
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*/
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vmov s0, 1.5
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vmov s1, 2.5
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vadd.f32 s2, s0, s1
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vmov s3, 4.0
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/* Compare two floating point registers. Stores results in fpscr:
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* (floating point status and control register).
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*/
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vcmp.f32 s2, s3
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/* Move the nzcv bits from fpscr to apsr */
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vmrs apsr_nzcv, fpscr
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/* This branch uses the Z bit of apsr, which was set accordingly. */
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LKMC_ASSERT(beq)
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/* Now the same from memory with vldr and vstr. */
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.data
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.align 4
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my_float_0:
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.float 1.5
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my_float_1:
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.float 2.5
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my_float_sum_expect:
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.float 4.0
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.bss
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my_float_sum:
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.skip 4
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.text
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ldr r0, =my_float_0
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vldr s0, [r0]
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ldr r0, =my_float_1
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vldr s1, [r0]
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vadd.f32 s2, s0, s1
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ldr r0, =my_float_sum
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vstr.f32 s2, [r0]
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LKMC_ASSERT_MEMCMP(my_float_sum, my_float_sum_expect, =4)
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#if 0
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/* We can't do pseudo vldr as for ldr, fails with:
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* Error: cannot represent CP_OFF_IMM relocation in this object file format
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* It works on ARMv8 however, so the relocation must have been added.
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*/
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vldr s0, my_float_0
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#endif
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/* Minimal double precision floating point example. */
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vmov.f64 d0, 1.5
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vmov.f64 d1, 2.5
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vadd.f64 d2, d0, d1
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vmov.f64 d3, 4.0
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vcmp.f64 d2, d3
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vmrs apsr_nzcv, fpscr
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LKMC_ASSERT(beq)
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/* vmov can also move to general purpose registers.
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*
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* Just remember that we can't use float immediates with general purpose registers:
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* https://stackoverflow.com/questions/6514537/how-do-i-specify-immediate-floating-point-numbers-with-inline-assembly/52906126#52906126
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*/
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mov r1, 2
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mov r0, 1
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vmov s0, r0
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vmov s1, s0
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vmov r1, s1
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LKMC_ASSERT_EQ_REG(r0, r1)
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LKMC_EPILOGUE
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