mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-25 19:21:35 +01:00
87 lines
2.2 KiB
ArmAsm
87 lines
2.2 KiB
ArmAsm
/* https://github.com/cirosantilli/arm-assembly-cheat#advanced-simd-instructions */
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#include "common.h"
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ENTRY
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/* 4x 32-bit integer add.
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*
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* s stands for single == 32 bits.
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*
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* 1 in ld1 means to load just one register, see:
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* https://github.com/cirosantilli/arm-assembly-cheat#simd-interleaving
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*/
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.data
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u32_0: .word 0xF111F111, 0xF222F222, 0xF333F333, 0xF444F444
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u32_1: .word 0x15551555, 0x16661666, 0x17771777, 0x18881888
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u32_sum_expect: .word 0x06670666, 0x08890888, 0x0AAB0AAA, 0x0CCD0CCC
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.bss
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u32_sum: .skip 16
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.text
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adr x0, u32_0
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ld1 {v0.4s}, [x0]
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adr x1, u32_1
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ld1 {v1.4s}, [x1]
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add v2.4s, v0.4s, v1.4s
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adr x0, u32_sum
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st1 {v2.4s}, [x0]
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ASSERT_MEMCMP(u32_sum, u32_sum_expect, 0x10)
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/* 2x 64-bit integer add.
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*
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* d stands for double == 64 bits.
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*/
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.data
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u64_0: .quad 0xF1111111F1111111, 0xF2222222F2222222
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u64_1: .quad 0x1555555515555555, 0x1666666616666666
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u64_sum_expect: .quad 0x0666666706666666, 0x0888888908888888
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.bss
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u64_sum: .skip 16
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.text
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adr x0, u64_0
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ld1 {v0.2d}, [x0]
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adr x1, u64_1
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ld1 {v1.2d}, [x1]
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add v2.2d, v0.2d, v1.2d
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adr x0, u64_sum
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st1 {v2.2d}, [x0]
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ASSERT_MEMCMP(u64_sum, u64_sum_expect, 0x10)
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/* 4x 32-bit float add.
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*
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* The only difference between the integer point version
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* is that we use fadd instead of add.
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*/
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.data
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f32_0: .float 1.5, 2.5, 3.5, 4.5
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f32_1: .float 5.5, 6.5, 7.5, 8.5
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f32_sum_expect: .float 7.0, 9.0, 11.0, 13.0
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.bss
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f32_sum: .skip 16
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.text
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adr x0, f32_0
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ld1 {v0.4s}, [x0]
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adr x1, f32_1
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ld1 {v1.4s}, [x1]
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fadd v2.4s, v0.4s, v1.4s
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adr x0, f32_sum
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st1 {v2.4s}, [x0]
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ASSERT_MEMCMP(f32_sum, f32_sum_expect, 0x10)
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/* 2x 64-bit float add. */
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.data
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f64_0: .double 1.5, 2.5
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f64_1: .double 5.5, 6.5
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f64_sum_expect: .double 7.0, 9.0
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.bss
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f64_sum: .skip 16
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.text
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adr x0, f64_0
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ld1 {v0.2d}, [x0]
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adr x1, f64_1
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ld1 {v1.2d}, [x1]
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fadd v2.2d, v0.2d, v1.2d
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adr x0, f64_sum
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st1 {v2.2d}, [x0]
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ASSERT_MEMCMP(f64_sum, f64_sum_expect, 0x10)
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EXIT
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