mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-22 17:55:57 +01:00
40 lines
1.6 KiB
Diff
40 lines
1.6 KiB
Diff
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
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index 05c38e011..0e0a719e4 100644
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--- a/configs/common/CacheConfig.py
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+++ b/configs/common/CacheConfig.py
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@@ -132,6 +132,11 @@ def config_cache(options, system):
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iwalkcache = None
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dwalkcache = None
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+ dcache_mon = CommMonitor()
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+ dcache_real = dcache
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+ dcache_mon.master = dcache.cpu_side
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+ dcache = dcache_mon
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+
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if options.memchecker:
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dcache_mon = MemCheckerMonitor(warn_only=True)
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dcache_real = dcache
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@@ -170,6 +175,9 @@ def config_cache(options, system):
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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iwalkcache, dwalkcache)
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+ system.cpu[i].dcache = dcache_real
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+ system.cpu[i].dcache_mon = dcache_mon
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+
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if options.memchecker:
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# The mem_side ports of the caches haven't been connected yet.
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# Make sure connectAllPorts connects the right objects.
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diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
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index e487cbb6b..cef5d3791 100644
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--- a/src/cpu/BaseCPU.py
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+++ b/src/cpu/BaseCPU.py
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@@ -214,7 +214,7 @@ class BaseCPU(ClockedObject):
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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- self.dcache_port = dc.cpu_side
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+ self.dcache_port = dc.slave
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self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
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if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
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if iwc and dwc:
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