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linux-kernel-module-cheat/gem5-se-py-page-translation.html
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<meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. EVERYTHING is built from source. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
<title>Linux Kernel Module Cheat</title>
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</head>
<body id="gem5-se-py-page-translation" class="article">
<div id="header">
<h1>Linux Kernel Module Cheat</h1>
</div>
<div id="content">
<div class="sect5">
<h6 id="gem5-se-py-page-translation"><a class="anchor" href="#gem5-se-py-page-translation"></a><a class="link" href="#gem5-se-py-page-translation">24.22.4.1.4. gem5 se.py page translation</a></h6>
<div class="paragraph">
<p>Happens on <code>EmulationPageTable</code>, and seems to happen atomically without making any extra memory requests.</p>
</div>
<div class="paragraph">
<p>TODO confirm from code, notably by seeing where the translation table is set.</p>
</div>
<div class="paragraph">
<p>But we can confirm with logging with:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>--trace DRAM,ExecAll,FmtFlag</pre>
</div>
</div>
<div class="paragraph">
<p>which gives</p>
</div>
<div class="literalblock">
<div class="content">
<pre> 0: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x78
0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue : movz x0, #1, #0 : IntAlu : D=0x0000000000000001 flags=(IsInteger)
500: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x7c
500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 : adr x1, #28 : IntAlu : D=0x0000000000400098 flags=(IsInteger)
1000: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x80
1000: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0xa0
1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8 : ldr w2, #4194464 : MemRead : D=0x0000000000000006 A=0x4000a0 flags=(IsInteger|IsMemRef|IsLoad)
1500: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x84
1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12 : movz x8, #64, #0 : IntAlu : D=0x0000000000000040 flags=(IsInteger)
2000: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x88
2000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+16 : svc #0x0 : IntAlu : flags=(IsSerializeAfter|IsNonSpeculative|IsSyscall)
hello
2500: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x8c
2500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+20 : movz x0, #0, #0 : IntAlu : D=0x0000000000000000 flags=(IsInteger)
3000: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x90
3000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+24 : movz x8, #93, #0 : IntAlu : D=0x000000000000005d flags=(IsInteger)
3500: DRAM: system.mem_ctrls: recvAtomic: ReadReq 0x94
3500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+28 : svc #0x0 : IntAlu : flags=(IsSerializeAfter|IsNonSpeculative|IsSyscall)
Exiting @ tick 3500 because exiting with last active thread context
3500: DRAM: system.mem_ctrls_0: Computing stats due to a dump callback
3500: DRAM: system.mem_ctrls_1: Computing stats due to a dump callback</pre>
</div>
</div>
<div class="paragraph">
<p>So we see that before every instruction execution there was a DRAM event! Also, each read happens 4 bytes after the previous one, which is consistent with instruction fetches.</p>
</div>
<div class="paragraph">
<p>The DRAM addresses are very close to zero e.g. <code>0x78</code> for the first instruction, and therefore we guess that they are physical since the ELF entry point is much higher:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>./run-toolchain --arch aarch64 readelf -- -h "$(./getvar --arch aarch64 userland_build_dir)/arch/aarch64/freestanding/linux/hello.out</pre>
</div>
</div>
<div class="paragraph">
<p>at:</p>
</div>
<div class="literalblock">
<div class="content">
<pre> Entry point address: 0x400078</pre>
</div>
</div>
<div class="paragraph">
<p>For LDR, we see that there was an extra DRAM read as well after the fetch read, as expected.</p>
</div>
<div class="paragraph">
<p>Tested in gem5 b4879ae5b0b6644e6836b0881e4da05c64a6550d.</p>
</div>
<div class="ulist">
<ul>
</ul>
</div>
</div>
<div class="paragraph nav-footer">
<p> Previous: <a href="atomicsimplecpu-memory-access.html">AtomicSimpleCPU memory access</a> | ↑ Up: <a href="gem5-event-queue-atomicsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis</a> →</p>
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