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linux-kernel-module-cheat/aarch64-baremetal-neon-setup.html
Ciro Santilli 0a2a05fe28 8e6cdcb14b
2025-05-10 07:50:53 +01:00

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<meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. EVERYTHING is built from source. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
<title>Linux Kernel Module Cheat</title>
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</head>
<body id="aarch64-baremetal-neon-setup" class="article">
<div id="header">
<h1>Linux Kernel Module Cheat</h1>
</div>
<div id="content">
<div class="sect3">
<h4 id="aarch64-baremetal-neon-setup"><a class="anchor" href="#aarch64-baremetal-neon-setup"></a><a class="link" href="#aarch64-baremetal-neon-setup">33.11.2. aarch64 baremetal NEON setup</a></h4>
<div class="paragraph">
<p>Inside <a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/baremetal/lib/aarch64.S">baremetal/lib/aarch64.S</a> there is a chunk of code that enables floating point operations:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>mov x1, 0x3 &lt;&lt; 20
msr cpacr_el1, x1
isb</pre>
</div>
</div>
<div class="paragraph">
<p>CPACR_EL1 is documented at <a href="armarm8.html">ARMv8 architecture reference manual</a> D10.2.29 "CPACR_EL1, Architectural Feature Access Control Register".</p>
</div>
<div class="paragraph">
<p>Here we touch the CPACR_EL1.FPEN bits to 3, which enable floating point operations:</p>
</div>
<div class="quoteblock">
<blockquote>
<div class="paragraph">
<p>11 This control does not cause any instructions to be trapped.</p>
</div>
</blockquote>
</div>
<div class="paragraph">
<p>We later also added an enable for the CPACR_EL1.ZEN bits, which are needed for <a href="arm-sve.html">ARM SVE</a>.</p>
</div>
<div class="paragraph">
<p>Without CPACR_EL1.FPEN, the <code>printf</code>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>printf("got: %c\n", c);</pre>
</div>
</div>
<div class="paragraph">
<p>compiled to a:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>str q0, [sp, #80]</pre>
</div>
</div>
<div class="paragraph">
<p>which uses NEON registers, and goes into an exception loop.</p>
</div>
<div class="paragraph">
<p>It was a bit confusing because there was a previous <code>printf</code>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>printf("enter a character\n");</pre>
</div>
</div>
<div class="paragraph">
<p>which did not blow up because GCC compiles it into <code>puts</code> directly since it has no arguments, and that does not generate NEON instructions.</p>
</div>
<div class="paragraph">
<p>The last instructions ran was found with:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>while(1)
stepi
end</pre>
</div>
</div>
<div class="paragraph">
<p>or by hacking the QEMU CLI to contain:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>-D log.log -d in_asm</pre>
</div>
</div>
<div class="paragraph">
<p>I could not find any previous NEON instruction executed so this led me to suspect that some NEON initialization was required:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dai0527a/DAI0527A_baremetal_boot_code_for_ARMv8_A_processors.pdf" class="bare">http://infocenter.arm.com/help/topic/com.arm.doc.dai0527a/DAI0527A_baremetal_boot_code_for_ARMv8_A_processors.pdf</a> "Bare-metal Boot Code for ARMv8-A Processors"</p>
</li>
<li>
<p><a href="https://community.arm.com/processors/f/discussions/5409/how-to-enable-neon-in-cortex-a8" class="bare">https://community.arm.com/processors/f/discussions/5409/how-to-enable-neon-in-cortex-a8</a></p>
</li>
<li>
<p><a href="https://stackoverflow.com/questions/19231197/enable-neon-on-arm-cortex-a-series" class="bare">https://stackoverflow.com/questions/19231197/enable-neon-on-arm-cortex-a-series</a></p>
</li>
</ul>
</div>
<div class="paragraph">
<p>We then tried to copy the code from the "Bare-metal Boot Code for ARMv8-A Processors" document:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>// Disable trapping of accessing in EL3 and EL2.
MSR CPTR_EL3, XZR
MSR CPTR_EL3, XZR
// Disable access trapping in EL1 and EL0.
MOV X1, #(0x3 &lt;&lt; 20) // FPEN disables trapping to EL1.
MSR CPACR_EL1, X1
ISB</pre>
</div>
</div>
<div class="paragraph">
<p>but it entered an exception loop at <code>MSR CPTR_EL3, XZR</code>.</p>
</div>
<div class="paragraph">
<p>We then found out that QEMU <a href="arm-exception-levels.html">starts in EL1</a>, and so we kept just the EL1 part, and it worked. Related:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><a href="https://stackoverflow.com/questions/42824706/qemu-system-aarch64-entering-el1-when-emulating-a53-power-up" class="bare">https://stackoverflow.com/questions/42824706/qemu-system-aarch64-entering-el1-when-emulating-a53-power-up</a></p>
</li>
<li>
<p><a href="https://stackoverflow.com/questions/37299524/neon-support-in-armv8-system-mode-qemu" class="bare">https://stackoverflow.com/questions/37299524/neon-support-in-armv8-system-mode-qemu</a></p>
</li>
</ul>
</div>
<div class="ulist">
<ul>
</ul>
</div>
</div>
<div class="paragraph nav-footer">
<p> Previous: <a href="find-the-uart-address.html">Find the UART address</a> | ↑ Up: <a href="how-we-got-some-baremetal-stuff-to-work.html">How we got some baremetal stuff to work</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="baremetal-tests.html">Baremetal tests</a> →</p>
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