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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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614 lines
37 KiB
HTML
614 lines
37 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. EVERYTHING is built from source. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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|
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</head>
|
||
<body id="timingsimplecpu-analysis-1" class="article">
|
||
<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect5">
|
||
<h6 id="timingsimplecpu-analysis-1"><a class="anchor" href="#timingsimplecpu-analysis-1"></a><a class="link" href="#timingsimplecpu-analysis-1">24.22.4.2.2. TimingSimpleCPU analysis #1</a></h6>
|
||
<div class="paragraph">
|
||
<p>Backtrace:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>EventManager::schedule
|
||
DRAMCtrl::Rank::startup
|
||
DRAMCtrl::startup</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Snippets:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>void
|
||
DRAMCtrl::startup()
|
||
{
|
||
// remember the memory system mode of operation
|
||
isTimingMode = system()->isTimingMode();
|
||
|
||
if (isTimingMode) {
|
||
// timestamp offset should be in clock cycles for DRAMPower
|
||
timeStampOffset = divCeil(curTick(), tCK);
|
||
|
||
// update the start tick for the precharge accounting to the
|
||
// current tick
|
||
for (auto r : ranks) {
|
||
r->startup(curTick() + tREFI - tRP);
|
||
}
|
||
|
||
// shift the bus busy time sufficiently far ahead that we never
|
||
// have to worry about negative values when computing the time for
|
||
// the next request, this will add an insignificant bubble at the
|
||
// start of simulation
|
||
nextBurstAt = curTick() + tRP + tRCD;
|
||
}
|
||
}</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>which then calls:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>void
|
||
DRAMCtrl::Rank::startup(Tick ref_tick)
|
||
{
|
||
assert(ref_tick > curTick());
|
||
|
||
pwrStateTick = curTick();
|
||
|
||
// kick off the refresh, and give ourselves enough time to
|
||
// precharge
|
||
schedule(refreshEvent, ref_tick);
|
||
}</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p><code>DRAMCtrl::startup</code> is itself a <code>SimObject</code> method exposed to Python and called from <code>simulate</code> in <code>src/python/m5/simulate.py</code>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>def simulate(*args, **kwargs):
|
||
global need_startup
|
||
|
||
if need_startup:
|
||
root = objects.Root.getInstance()
|
||
for obj in root.descendants(): obj.startup()</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>where <code>simulate</code> happens after <code>m5.instantiate</code>, and both are called directly from the toplevel scripts, e.g. for se.py in <code>configs/common/Simulation.py</code>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>def run(options, root, testsys, cpu_class):
|
||
...
|
||
exit_event = m5.simulate()</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>By looking up some variable definitions in the source, we now we see some memory parameters clearly:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>ranks: <code>std::vector<DRAMCtrl::Rank*></code> with 2 elements. TODO why do we have 2? What does it represent? Likely linked to <a href="gem5-config-ini.html"><code>config.ini</code></a> at <code>system.mem_ctrls.ranks_per_channel=2</code>: <a href="https://en.wikipedia.org/wiki/Memory_rank" class="bare">https://en.wikipedia.org/wiki/Memory_rank</a></p>
|
||
</li>
|
||
<li>
|
||
<p><code>tCK=1250</code>, <code>tREFI=7800000</code>, <code>tRP=13750</code>, <code>tRCD=13750</code>: all defined in a single code location with a comment:</p>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> /**
|
||
* Basic memory timing parameters initialized based on parameter
|
||
* values.
|
||
*/</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Their values can be seen under <code>config.ini</code> and they are documented in <code>src/mem/DRAMCtrl.py</code> e.g.:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> # the base clock period of the DRAM
|
||
tCK = Param.Latency("Clock period")
|
||
|
||
# minimum time between a precharge and subsequent activate
|
||
tRP = Param.Latency("Row precharge time")
|
||
|
||
# the amount of time in nanoseconds from issuing an activate command
|
||
# to the data being available in the row buffer for a read/write
|
||
tRCD = Param.Latency("RAS to CAS delay")
|
||
|
||
# refresh command interval, how often a "ref" command needs
|
||
# to be sent. It is 7.8 us for a 64ms refresh requirement
|
||
tREFI = Param.Latency("Refresh command interval")</pre>
|
||
</div>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>So we realize that we are going into deep DRAM modelling, more detail that a mere mortal should ever need to know.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p><code>curTick() + tREFI - tRP = 0 + 7800000 - 13750 = 7786250</code> which is when that <code>refreshEvent</code> was scheduled. Our simulation ends way before that point however, so we will never know what it did thank God.</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>← Previous: <a href="timingsimplecpu-analysis-0.html">TimingSimpleCPU analysis #0</a> | ↑ Up: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="timingsimplecpu-analysis-2.html">TimingSimpleCPU analysis #2</a> →</p>
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