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linux-kernel-module-cheat/gem5-instruction-definitions.html
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<meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. EVERYTHING is built from source. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
<title>Linux Kernel Module Cheat</title>
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</head>
<body id="gem5-instruction-definitions" class="article">
<div id="header">
<h1>Linux Kernel Module Cheat</h1>
</div>
<div id="content">
<div class="sect3">
<h4 id="gem5-instruction-definitions"><a class="anchor" href="#gem5-instruction-definitions"></a><a class="link" href="#gem5-instruction-definitions">24.22.5. gem5 instruction definitions</a></h4>
<div class="paragraph">
<p>This is one of the parts of gem5 that rely on semi-useless <a href="gem5-code-generation.html">code generation</a> inside the <code>.isa</code> sublanguage.</p>
</div>
<div class="paragraph">
<p>Which is mostly Python, with some magic letters thrown in for good measure.</p>
</div>
<div class="paragraph">
<p>The class definitions get all dumped into one humongous C++ include file:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>build/ARM/arch/arm/generated/exec-ns.cc.inc</pre>
</div>
</div>
<div class="paragraph">
<p>That file defines the key methods of each instruction, e.g. the ARM immediate <a href="userland-assembly.html">ADD instruction</a> has its <code>execute</code> method defined there:</p>
</div>
<div class="literalblock">
<div class="content">
<pre> Fault AddImm::execute(
ExecContext *xc, Trace::InstRecord *traceData) const</pre>
</div>
</div>
<div class="paragraph">
<p>or for example the key methods of an <a href="arm-str-instruction.html">ARM 64-bit (X) STR with an immediate offset</a> (<code>STR &lt;Wt&gt;, [&lt;Xn|SP&gt;], #&lt;simm&gt;</code>):</p>
</div>
<div class="literalblock">
<div class="content">
<pre> Fault STRX64_IMM::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
Fault STRX64_IMM::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
Fault STRX64_IMM::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
}</pre>
</div>
</div>
<div class="paragraph">
<p>We also notice that the key argument passed to those instructions is of type <code>ExecContext</code>, which is discussed further at: <a href="gem5-execcontext.html">Section 24.22.6.3, &#8220;gem5 <code>ExecContext</code>&#8221;</a>.</p>
</div>
<div class="paragraph">
<p>The file is an include so that compilation can be split up into chunks by the autogenerated includers</p>
</div>
<div class="literalblock">
<div class="content">
<pre>build/ARM/arch/arm/generated/generic_cpu_1.cc
build/ARM/arch/arm/generated/generic_cpu_2.cc
...</pre>
</div>
</div>
<div class="paragraph">
<p>via the <code>__SPLIT</code> macro as in:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>#include "exec-g.cc.inc"
#include "cpu/exec_context.hh"
#include "decoder.hh"
namespace ArmISAInst {
#define __SPLIT 1
#include "exec-ns.cc.inc"
}</pre>
</div>
</div>
<div class="paragraph">
<p>This is likely done to not overload the C++ compiler? But sure enough overloads IDEs and GDB which takes forever to load the source of any frames going through it.</p>
</div>
<div class="paragraph">
<p>We should split that file into one per class for the love of God.</p>
</div>
<div class="paragraph">
<p>The autogenerated instruction class declarations can be found at:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>build/ARM/arch/arm/generated/decoder-ns.hh.inc</pre>
</div>
</div>
<div class="paragraph">
<p>and the autogenerated bulk of the decoder:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>build/ARM/arch/arm/generated/decoder-ns.cc.inc</pre>
</div>
</div>
<div class="paragraph">
<p>which also happens to contain the constructor definitions of the instruction classes, e.g. for the ADD immediate because why not:</p>
</div>
<div class="literalblock">
<div class="content">
<pre> AddImm::AddImm(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint32_t _imm,
bool _rotC)</pre>
</div>
</div>
<div class="paragraph">
<p>The above files get tied in the autogenerated:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>build/ARM/arch/arm/generated/decoder.hh</pre>
</div>
</div>
<div class="paragraph">
<p>which contains:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>#include "decoder-g.hh.inc"
namespace ArmISAInst {
#include "decoder-ns.hh.inc"
}</pre>
</div>
</div>
<div class="paragraph">
<p>Different instructions inherit form different classes, e.g. the ARM immediate ADD instruction is a <code>DataImmOp</code>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>class AddImm : public DataImmOp
{
public:
// Constructor
AddImm(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};</pre>
</div>
</div>
<div class="paragraph">
<p>and STRX64_IMM is an <code>ArmISA::MemoryImm64</code>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre> class STRX64_IMM : public ArmISA::MemoryImm64
{
public:
/// Constructor.
STRX64_IMM(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
void
annotateFault(ArmFault *fault) override
{
fault-&gt;annotate(ArmFault::SAS, 3);
fault-&gt;annotate(ArmFault::SSE, false);
fault-&gt;annotate(ArmFault::SRT, dest);
fault-&gt;annotate(ArmFault::SF, true);
fault-&gt;annotate(ArmFault::AR, false);
}
};</pre>
</div>
</div>
<div class="paragraph">
<p>but different memory instructions can have different base classes too e.g. <a href="arm-ldxr-and-stxr-instructions.html">STXR</a>:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>class STXRX64 : public ArmISA::MemoryEx64</pre>
</div>
</div>
<div class="paragraph">
<p>A summarized class hierarchy for the above is:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>StaticInst</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::ArmStaticInst</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::PredOp</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::DataImmOp</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::AddImm</code></p>
</li>
</ul>
</div>
</li>
<li>
<p><code>ArmISA::MightBeMicro64</code></p>
<div class="ulist">
<ul>
<li>
<p>ArmISA::Memory64</p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::MemoryImm64</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::MemoryEx64</code></p>
<div class="ulist">
<ul>
<li>
<p><code>ArmISA::STXRX64</code></p>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
</li>
</ul>
</div>
<div class="paragraph">
<p>Tested in gem5 b1623cb2087873f64197e503ab8894b5e4d4c7b4.</p>
</div>
<div class="ulist">
<ul>
<li>
<p><a href="gem5-execute-vs-initiateacc-vs-completeacc.html">gem5 &lt;code&gt;execute&lt;/code&gt; vs &lt;code&gt;initiateAcc&lt;/code&gt; vs &lt;code&gt;completeAcc&lt;/code</a>&gt;</p>
</li>
<li>
<p><a href="gem5-microops.html">gem5 microops</a></p>
</li>
</ul>
</div>
</div>
<div class="paragraph nav-footer">
<p> Previous: <a href="gem5-event-queue-derivo3cpu-syscall-emulation-freestanding-example-analysis-speculative.html">gem5 event queue DerivO3CPU syscall emulation freestanding example analysis: speculative</a> | ↑ Up: <a href="gem5-internals.html">gem5 internals</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-execute-vs-initiateacc-vs-completeacc.html">gem5 <code>execute</code> vs <code>initiateAcc</code> vs <code>completeAcc</code></a> →</p>
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