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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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657 lines
42 KiB
HTML
657 lines
42 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. EVERYTHING is built from source. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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</head>
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<body id="gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis" class="article">
|
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<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect4">
|
||
<h5 id="gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis"><a class="anchor" href="#gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis"></a><a class="link" href="#gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis">24.22.4.7. gem5 event queue MinorCPU syscall emulation freestanding example analysis</a></h5>
|
||
<div class="paragraph">
|
||
<p>The events <a href="gem5-event-queue-atomicsimplecpu-syscall-emulation-freestanding-example-analysis.html">for the Atomic CPU</a> were pretty simple: basically just ticks.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>But as we venture into <a href="gem5-cpu-types.html">more complex CPU models</a> such as <code>MinorCPU</code>, the events get much more complex and interesting.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The memory system system part must be similar to that of <code>TimingSimpleCPU</code> that we previously studied <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis</a>: the main thing we want to see is how the CPU pipeline speeds up execution by preventing some memory stalls.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The <a href="gem5-config-ini.html"><code>config.dot.svg</code></a> also indicates that: everything is exactly as in <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis-with-caches.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches</a>, except that the CPU is a <code>MinorCPU</code> instead of <code>TimingSimpleCPU</code>, and the <code>--caches</code> are now mandatory:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>./run \
|
||
--arch aarch64 \
|
||
--emulator gem5 \
|
||
--userland userland/arch/aarch64/freestanding/linux/hello.S \
|
||
--trace FmtFlag,Cache,Event,ExecAll,Minor \
|
||
--trace-stdout \
|
||
-- \
|
||
--cpu-type MinorCPU \
|
||
--caches \
|
||
;</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and here’s a handy link to the source: <a href="https://github.com/cirosantilli/linux-kernel-module-cheat/blob/master/userland/arch/aarch64/freestanding/linux/hello.S">userland/arch/aarch64/freestanding/linux/hello.S</a>.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>On LKMC ce3ea9faea95daf46dea80d4236a30a0891c3ca5 gem5 872cb227fdc0b4d60acc7840889d567a6936b6e1 we see the following.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>First there is a missed instruction fetch for the initial entry address which we know from <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis-with-caches.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches</a> is the virtual address 0x400078 which maps to physical 0x78:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 500: Cache: system.cpu.icache: access for ReadReq [40:7f] IF miss</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The memory request comes back later on at:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 77000: Cache: system.cpu.icache: recvTimingResp: Handling response ReadResp [40:7f] IF</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and soon after the CPU also ifetches across the barrier:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 79000: Cache: system.cpu.icache: access for ReadReq [80:bf] IF miss</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO why? We have 0x78 and 0x7c, and those should be it since we <a href="gem5-functional-units.html">are dual issue</a>, right? Is this prefetching at work?</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Later on we see the first instruction, our <a href="arm-mov-instruction.html">MOVZ</a>, was decoded:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 80000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/1/1.1 pc: 0x400078 (movz) to FU: 0</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and that issue succeeds, because the functional unit 0 (FU 0) is an <code>IntAlu</code> as shown at <a href="gem5-functional-units.html">gem5 functional units</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 80000: MinorExecute: system.cpu.execute: Issuing inst: 0/1.1/1/1.1 pc: 0x400078 (movz) into FU 0</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>At the very same tick, the second instruction is also decoded, our <a href="arm-adr-instruction.html">ADR</a>:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 80000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/1/2.2 pc: 0x40007c (adr) to FU: 0
|
||
80000: MinorExecute: system.cpu.execute: Can't issue as FU: 0 is already busy
|
||
80000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/1/2.2 pc: 0x40007c (adr) to FU: 1
|
||
80000: MinorExecute: system.cpu.execute: Issuing inst: 0/1.1/1/2.2 pc: 0x40007c (adr) into FU 1</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This is also an <code>IntAlu</code> instruction, and it can’t run on FU 0 because the first instruction is already running there. But to our luck, FU 1 is also an <code>IntAlu</code> unit, and so it runs there.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Crap, those Minor logs should say what <code>OpClass</code> each instruction is, that would make things clearer.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO what is that <code>0/1.1/1/1.1</code> notation that shows up everywhere? Must be important, let’s look at the source.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Soon after (3 ticks later, so guessing due to <code>opLat=3</code>?), the execution appears to be over already since we see the <code>ExecAll</code> come through, which generally happens at the very end:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 81500: MinorExecute: system.cpu.execute: Attempting to commit [tid:0]
|
||
81500: MinorExecute: system.cpu.execute: Committing micro-ops for interrupt[tid:0]
|
||
81500: MinorExecute: system.cpu.execute: Trying to commit canCommitInsts: 1
|
||
81500: MinorExecute: system.cpu.execute: Trying to commit from FUs
|
||
81500: MinorExecute: global: ExecContext setting PC: (0x400078=>0x40007c).(0=>1)
|
||
81500: MinorExecute: system.cpu.execute: Committing inst: 0/1.1/1/1.1 pc: 0x400078 (movz)
|
||
81500: MinorExecute: system.cpu.execute: Unstalling 0 for inst 0/1.1/1/1.1
|
||
81500: MinorExecute: system.cpu.execute: Completed inst: 0/1.1/1/1.1 pc: 0x400078 (movz)
|
||
81500: MinorScoreboard: system.cpu.execute.scoreboard0: Clearing inst: 0/1.1/1/1.1 pc: 0x400078 (movz) regIndex: 0 final numResults: 0
|
||
81500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue : movz x0, #1, #0 : IntAlu : D=0x0000000000000001 FetchSeq=1 CPSeq=1 flags=(IsInteger)
|
||
81500: MinorExecute: system.cpu.execute: Trying to commit canCommitInsts: 1
|
||
81500: MinorExecute: system.cpu.execute: Trying to commit from FUs
|
||
81500: MinorExecute: global: ExecContext setting PC: (0x40007c=>0x400080).(0=>1)
|
||
81500: MinorExecute: system.cpu.execute: Committing inst: 0/1.1/1/2.2 pc: 0x40007c (adr)
|
||
81500: MinorExecute: system.cpu.execute: Unstalling 1 for inst 0/1.1/1/2.2
|
||
81500: MinorExecute: system.cpu.execute: Completed inst: 0/1.1/1/2.2 pc: 0x40007c (adr)
|
||
81500: MinorScoreboard: system.cpu.execute.scoreboard0: Clearing inst: 0/1.1/1/2.2 pc: 0x40007c (adr) regIndex: 1 final numResults: 0
|
||
81500: MinorExecute: system.cpu.execute: Reached inst commit limit
|
||
81500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4 : adr x1, #28 : IntAlu : D=0x0000000000400098 FetchSeq=2 CPSeq=2 flags=(IsInteger)</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The ifetch for the third instruction returns at:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 129000: Cache: system.cpu.icache: recvTimingResp: Handling response ReadResp [80:bf] IF</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>so now we are ready to run the third and fourth instructions of the program:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> ldr x2, =len
|
||
mov x8, 64</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The <a href="arm-ldr-instruction.html">LDR</a> goes all the way down to FU 6 which is the memory one:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 0
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 0 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 1
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 1 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 2
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 2 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 3
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 3 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 4
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 4 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 5
|
||
132000: MinorExecute: system.cpu.execute: Can't issue as FU: 5 isn't capable
|
||
132000: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) to FU: 6
|
||
132000: MinorExecute: system.cpu.execute: Issuing inst: 0/1.1/2/3.3 pc: 0x400080 (ldr) into FU 6</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>and then the MOV issue follows soon afterwards (TODO why not at the same time like for the previous pair?):</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> 132500: MinorExecute: system.cpu.execute: Trying to issue inst: 0/1.1/2/4.4 pc: 0x400084 (movz) to FU: 0
|
||
132500: MinorExecute: system.cpu.execute: Issuing inst: 0/1.1/2/4.4 pc: 0x400084 (movz) into FU 0</pre>
|
||
</div>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis-hazard.html">gem5 event queue MinorCPU syscall emulation freestanding example analysis: hazard</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>← Previous: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis-with-caches-and-multiple-cpus-and-ruby.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs and Ruby</a> | ↑ Up: <a href="gem5-event-queue.html">gem5 event queue</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-event-queue-minorcpu-syscall-emulation-freestanding-example-analysis-hazard.html">gem5 event queue MinorCPU syscall emulation freestanding example analysis: hazard</a> →</p>
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