baremetal aarch64: create C version of multicore.S as well

Attempted to do the same for arm, but it failed.

baremetal/arch/arm/multicore.c

@@ -0,0 +1,37 @@
+/* https://cirosantilli.com/linux-kernel-module-cheat#arm-multicore */
+
+#include <lkmc.h>
+
+uint64_t spinlock = 0;
+
+__asm__(
+".syntax unified\n"
+".text\n"
+".global lkmc_cpu_not_0\n"
+"lkmc_cpu_not_0:\n"
+"    cmp r0, 1\n"
+"    bne .Lsleep_forever\n"
+"    ldr sp, =(stack_top - 0x1000)\n"
+"    bl main_cpu1\n"
+".Lsleep_forever:\n"
+"    wfe\n"
+"    b .Lsleep_forever\n"
+);
+
+static void main_cpu1(void) {
+    spinlock = 1;
+    lkmc_arm_aarch64_dmb(sy);
+    lkmc_arm_aarch64_sev();
+    while (1) {
+        lkmc_arm_aarch64_wfe();
+    }
+}
+
+int main(void) {
+#if !LKMC_GEM5
+    lkmc_arm_psci_cpu_on(1, (uint32_t)main_cpu1, 0);
+#endif
+    while (!spinlock) {
+        lkmc_arm_aarch64_wfe();
+    }
+}

baremetal/arch/arm/no_bootloader/multicore_asm.S

@@ -2,24 +2,25 @@
 
 #include <lkmc.h>
 
-LKMC_PROLOGUE
+.global lkmc_start
+lkmc_start:
     mov r0, 0
-    ldr r1, =spinlock
+    ldr r1, =.Lspinlock
     str r0, [r1]
     /* Get CPU ID. */
     mrc p15, 0, r1, c0, c0, 5
     ands r1, r1, 3
-    beq cpu0_only
+    beq .Lcpu0_only
 .Lcpu1_only:
     mov r0, 1
-    ldr r1, =spinlock
+    ldr r1, =.Lspinlock
     str r0, [r1]
     dmb sy
     sev
 .Lcpu1_sleep_forever:
     wfe
     b .Lcpu1_sleep_forever
-cpu0_only:
+.Lcpu0_only:
 #if !LKMC_GEM5
     /* PSCI CPU_ON. */
     ldr r0, =0x84000003
@@ -28,11 +29,12 @@ cpu0_only:
     mov r3, 0
     hvc 0
 #endif
-spinlock_start:
-    ldr r0, spinlock
+.Lspinlock_start:
+    ldr r0, .Lspinlock
     wfe
     cmp r0, 0
-    beq spinlock_start
-LKMC_EPILOGUE
-spinlock:
+    beq .Lspinlock_start
+    mov r0, 0
+    bl _exit
+.Lspinlock:
     .skip 4