arm baremetal: link back to svc answer

README.adoc

@@ -14842,9 +14842,8 @@ Bibliography:
 * https://github.com/torvalds/linux/blob/v4.20/arch/arm64/kernel/entry.S#L430 this is where the kernel defines the vector table
 * https://github.com/dwelch67/qemu_arm_samples/tree/07162ba087111e0df3f44fd857d1b4e82458a56d/swi01
 * https://github.com/NienfengYao/armv8-bare-metal/blob/572c6f95880e70aa92fe9fed4b8ad7697082a764/vector.S#L168
-* https://stackoverflow.com/questions/51094092/how-to-make-timer-irq-work-on-qemu-machine-virt-cpu-cortex-a57
+* https://stackoverflow.com/questions/24162109/arm-assembly-code-and-svc-numbering/57064062#57064062
 * https://stackoverflow.com/questions/44991264/armv8-exception-vectors-and-handling
-* https://stackoverflow.com/questions/44198483/arm-timers-and-interrupts
 
 ===== ARM ESR register
 
@@ -15011,6 +15010,11 @@ The key registers to keep in mind are:
 * `CNTV_CTL_EL0`: "Counter-timer Virtual Timer Control register"
 * `CNTV_CVAL_EL0`: "Counter-timer Virtual Timer CompareValue register". The interrupt happens when `CNTVCT_EL0` reaches the value in this register.
 
+Bibliography:
+
+* https://stackoverflow.com/questions/51094092/how-to-make-timer-irq-work-on-qemu-machine-virt-cpu-cortex-a57
+* https://stackoverflow.com/questions/44198483/arm-timers-and-interrupts
+
 ==== ARM baremetal bibliography
 
 First, also consider the userland bibliography: <<arm-assembly-bibliography>>.