mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-23 02:05:57 +01:00
aarch64 baremetal svc factored out for C and asm
This commit is contained in:
Ciro Santilli 六四事件 法轮功
@@ -7,6 +7,6 @@ main:
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/* test-gdb-result */
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cmp x1, #3
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beq 1f
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bl common_assert_fail
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bl lkmc_assert_fail
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1:
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ret
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@@ -1,29 +0,0 @@
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#ifndef COMMON_AARCH64_H
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#define COMMON_AARCH64_H
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#include <inttypes.h>
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#define SYSREG_READ(type, name) \
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type sysreg_ ## name ## _read(void) { \
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type name; \
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__asm__ __volatile__("mrs %0, " #name : "=r" (name) : : ); \
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return name; \
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}
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#define SYSREG_WRITE(type, name) \
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void sysreg_ ## name ## _write(type name) { \
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__asm__ __volatile__("msr " #name ", %0" : : "r" (name) : ); \
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}
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#define SYSREG_READ_WRITE(name, type) \
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SYSREG_READ(name, type) \
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SYSREG_WRITE(name, type)
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SYSREG_READ_WRITE(uint32_t, daif)
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SYSREG_READ_WRITE(uint32_t, spsel)
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SYSREG_READ_WRITE(uint64_t, sp_el1)
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SYSREG_READ_WRITE(uint64_t, vbar_el1)
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#define SVC(immediate) __asm__ __volatile__("svc " #immediate : : : )
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#endif
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@@ -12,7 +12,7 @@ main:
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fmov d3, #4.0
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fcmp d2, d3
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beq 1f
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bl common_assert_fail
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bl lkmc_assert_fail
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1:
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/* Now in 32-bit. */
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@@ -26,7 +26,7 @@ main:
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fmov s3, #4.0
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fcmp s2, s3
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beq 1f
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bl common_assert_fail
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bl lkmc_assert_fail
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1:
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/* Higher registers. */
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@@ -40,6 +40,6 @@ main:
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/* test-gdb-d31 */
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fcmp d30, d31
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beq 1f
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bl common_assert_fail
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bl lkmc_assert_fail
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1:
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ret
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@@ -2,33 +2,22 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <common.h>
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#include "common_aarch64.h"
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#include <lkmc.h>
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void handle_svc() {
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exit(0);
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int myvar = 0;
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void lkmc_vector_trap_handler(LkmcVectorExceptionFrame *exception) {
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puts("trap handler");
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myvar = 1;
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}
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int main(void) {
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/* View initial register values. */
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printf("daif 0x%" PRIx32 "\n", sysreg_daif_read());
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printf("spsel 0x%" PRIx32 "\n", sysreg_spsel_read());
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printf("vbar_el1 0x%" PRIx64 "\n", sysreg_vbar_el1_read());
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/* Set registers to the values that we need. */
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sysreg_daif_write(0);
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sysreg_vbar_el1_write(0);
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printf("daif 0x%" PRIx32 "\n", sysreg_daif_read());
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printf("spsel 0x%" PRIx32 "\n", sysreg_spsel_read());
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printf("vbar_el1 0x%" PRIx64 "\n", sysreg_vbar_el1_read());
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/* TODO this breaks execution because reading system registers that end
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* in ELx "trap", leading into an exception on the upper EL.
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*/
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/*printf("sp_el1 0x%" PRIx64 "\n", sysreg_sp_el1_read());*/
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/*SVC(0);*/
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/* Should never be reached. */
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/*common_assert_fail();*/
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/* View initial relevant register values. */
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printf("daif 0x%" PRIx32 "\n", lkmc_sysreg_daif_read());
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printf("spsel 0x%" PRIx32 "\n", lkmc_sysreg_spsel_read());
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printf("vbar_el1 0x%" PRIx64 "\n", lkmc_sysreg_vbar_el1_read());
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lkmc_assert(myvar == 0);
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LKMC_SVC(0);
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lkmc_assert(myvar == 1);
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return 0;
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}
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@@ -1,11 +1,7 @@
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/* TODO factor it out to make reusable. */
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#include <lkmc.h>
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.global main
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main:
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/* Load the vector table. */
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ldr x0, =vector_table
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msr vbar_el1, x0
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/* Do the svc. */
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svc 0
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@@ -14,13 +10,13 @@ main:
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ldr x1, mynewvar
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cmp x0, x1
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beq 1f
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bl common_assert_fail
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bl lkmc_assert_fail
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1:
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/* Go home. */
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ret
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common_trap_handler:
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LKMC_GLOBAL(lkmc_vector_trap_handler)
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/* Modify myvar as a visible side effect. */
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ldr x0, mynewvar
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ldr x1, =myvar
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@@ -31,210 +27,3 @@ myvar:
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.quad 0x0
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mynewvar:
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.quad 0x12346789ABCDEF0
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/* .h
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*
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* Adapted from: https://github.com/takeharukato/sample-tsk-sw/blob/ce7973aa5d46c9eedb58309de43df3b09d4f8d8d/hal/aarch64/vector.S
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*/
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#define AARCH64_EXC_SYNC_SP0 (0x1)
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#define AARCH64_EXC_IRQ_SP0 (0x2)
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#define AARCH64_EXC_FIQ_SP0 (0x3)
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#define AARCH64_EXC_SERR_SP0 (0x4)
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#define AARCH64_EXC_SYNC_SPX (0x11)
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#define AARCH64_EXC_IRQ_SPX (0x12)
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#define AARCH64_EXC_FIQ_SPX (0x13)
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#define AARCH64_EXC_SERR_SPX (0x14)
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#define AARCH64_EXC_SYNC_AARCH64 (0x21)
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#define AARCH64_EXC_IRQ_AARCH64 (0x22)
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#define AARCH64_EXC_FIQ_AARCH64 (0x23)
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#define AARCH64_EXC_SERR_AARCH64 (0x24)
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#define AARCH64_EXC_SYNC_AARCH32 (0x31)
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#define AARCH64_EXC_IRQ_AARCH32 (0x32)
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#define AARCH64_EXC_FIQ_AARCH32 (0x33)
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#define AARCH64_EXC_SERR_AARCH32 (0x34)
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#if !defined(__ASSEMBLER__)
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#include <stdint.h>
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typedef struct _exception_frame{
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uint64_t exc_type;
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uint64_t exc_esr;
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uint64_t exc_sp;
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uint64_t exc_elr;
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uint64_t exc_spsr;
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uint64_t x0;
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uint64_t x1;
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uint64_t x2;
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uint64_t x3;
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uint64_t x4;
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uint64_t x5;
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uint64_t x6;
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uint64_t x7;
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uint64_t x8;
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uint64_t x9;
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uint64_t x10;
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uint64_t x11;
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uint64_t x12;
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uint64_t x13;
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uint64_t x14;
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uint64_t x15;
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uint64_t x16;
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uint64_t x17;
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uint64_t x18;
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uint64_t x19;
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uint64_t x20;
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uint64_t x21;
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uint64_t x22;
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uint64_t x23;
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uint64_t x24;
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uint64_t x25;
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uint64_t x26;
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uint64_t x27;
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uint64_t x28;
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uint64_t x29;
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uint64_t x30;
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} exception_frame;
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void common_trap_handler(exception_frame *exception);
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#endif
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/* .S */
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#define EXC_FRAME_SIZE (288) /* sizeof(exception_frame) */
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#define EXC_EXC_TYPE_OFFSET (0) /* offsetof(exception_frame, exc_type) */
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#define EXC_EXC_ESR_OFFSET (8) /* offsetof(exception_frame, exc_esr) */
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#define EXC_EXC_SP_OFFSET (16) /* offsetof(exception_frame, exc_sp) */
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#define EXC_EXC_ELR_OFFSET (24) /* offsetof(exception_frame, exc_elr) */
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#define EXC_EXC_SPSR_OFFSET (32) /* offsetof(exception_frame, exc_spsr) */
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#define BUILD_TRAPFRAME(exc_type) \
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stp x29, x30, [sp, -16]!; \
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stp x27, x28, [sp, -16]!; \
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stp x25, x26, [sp, -16]!; \
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stp x23, x24, [sp, -16]!; \
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stp x21, x22, [sp, -16]!; \
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stp x19, x20, [sp, -16]!; \
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stp x17, x18, [sp, -16]!; \
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stp x15, x16, [sp, -16]!; \
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stp x13, x14, [sp, -16]!; \
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stp x11, x12, [sp, -16]!; \
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stp x9, x10, [sp, -16]!; \
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stp x7, x8, [sp, -16]!; \
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stp x5, x6, [sp, -16]!; \
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stp x3, x4, [sp, -16]!; \
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stp x1, x2, [sp, -16]!; \
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mrs x21, spsr_el1; \
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stp x21, x0, [sp, -16]!; \
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mrs x21, elr_el1; \
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stp xzr, x21, [sp, -16]!; \
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mov x21, (exc_type); \
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mrs x22, esr_el1; \
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stp x21, x22, [sp, -16]!
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#define STORE_TRAPED_SP \
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mrs x21, sp_el0; \
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str x21, [sp, EXC_EXC_SP_OFFSET]
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#define CALL_COMMON_TRAP_HANDLER \
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mov x0, sp; \
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bl common_trap_handler
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#define STORE_NESTED_SP \
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mov x21, sp; \
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add x21, x21, EXC_FRAME_SIZE; \
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str x21, [sp, EXC_EXC_SP_OFFSET]
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#define RESTORE_TRAPED_SP \
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ldr x21, [sp, EXC_EXC_SP_OFFSET]; \
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msr sp_el0, x21
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#define RESTORE_TRAPFRAME \
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add sp, sp, 16; \
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ldp x21, x22, [sp], 16; \
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msr elr_el1, x22; \
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ldp x21, x0, [sp], 16; \
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msr spsr_el1, x21; \
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ldp x1, x2, [sp], 16; \
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ldp x3, x4, [sp], 16; \
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ldp x5, x6, [sp], 16; \
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ldp x7, x8, [sp], 16; \
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ldp x9, x10, [sp], 16; \
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ldp x11, x12, [sp], 16; \
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ldp x13, x14, [sp], 16; \
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ldp x15, x16, [sp], 16; \
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ldp x17, x18, [sp], 16; \
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ldp x19, x20, [sp], 16; \
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ldp x21, x22, [sp], 16; \
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ldp x23, x24, [sp], 16; \
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ldp x25, x26, [sp], 16; \
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ldp x27, x28, [sp], 16; \
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ldp x29, x30, [sp], 16; \
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eret
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#define VECTOR_ENTRY(func_name) \
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.align 7; \
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b func_name
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#define VECTOR_FUNC_ALIGN .align 2
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#define VECTOR_FUNC(func_name, func_id) \
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VECTOR_FUNC_ALIGN; \
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func_name:; \
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BUILD_TRAPFRAME(func_id); \
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STORE_TRAPED_SP; \
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CALL_COMMON_TRAP_HANDLER; \
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RESTORE_TRAPED_SP; \
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RESTORE_TRAPFRAME
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#define VECTOR_FUNC_NESTED(func_name, func_id) \
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VECTOR_FUNC_ALIGN; \
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func_name:; \
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BUILD_TRAPFRAME(func_id); \
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STORE_NESTED_SP; \
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CALL_COMMON_TRAP_HANDLER; \
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RESTORE_TRAPFRAME
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.align 11
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.global vector_table
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vector_table:
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VECTOR_ENTRY(_curr_el_sp0_sync)
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VECTOR_ENTRY(_curr_el_sp0_irq)
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VECTOR_ENTRY(_curr_el_sp0_fiq)
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VECTOR_ENTRY(_curr_el_sp0_serror)
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VECTOR_ENTRY(_curr_el_spx_sync)
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VECTOR_ENTRY(_curr_el_spx_irq)
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VECTOR_ENTRY(_curr_el_spx_fiq)
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VECTOR_ENTRY(_curr_el_spx_serror)
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VECTOR_ENTRY(_lower_el_aarch64_sync)
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VECTOR_ENTRY(_lower_el_aarch64_irq)
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VECTOR_ENTRY(_lower_el_aarch64_fiq)
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VECTOR_ENTRY(_lower_el_aarch64_serror)
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VECTOR_ENTRY(_lower_el_aarch32_sync)
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VECTOR_ENTRY(_lower_el_aarch32_irq)
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VECTOR_ENTRY(_lower_el_aarch32_fiq)
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VECTOR_ENTRY(_lower_el_aarch32_serror)
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VECTOR_FUNC(_curr_el_sp0_sync, AARCH64_EXC_SYNC_SP0)
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VECTOR_FUNC(_curr_el_sp0_irq, AARCH64_EXC_IRQ_SP0)
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VECTOR_FUNC(_curr_el_sp0_fiq, AARCH64_EXC_FIQ_SP0)
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VECTOR_FUNC(_curr_el_sp0_serror, AARCH64_EXC_SERR_SP0)
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VECTOR_FUNC_NESTED(_curr_el_spx_sync, AARCH64_EXC_SYNC_SPX)
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VECTOR_FUNC_NESTED(_curr_el_spx_irq, AARCH64_EXC_IRQ_SPX)
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VECTOR_FUNC_NESTED(_curr_el_spx_fiq, AARCH64_EXC_FIQ_SPX)
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VECTOR_FUNC_NESTED(_curr_el_spx_serror, AARCH64_EXC_SERR_SPX)
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VECTOR_FUNC(_lower_el_aarch64_sync, AARCH64_EXC_SYNC_AARCH64)
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VECTOR_FUNC(_lower_el_aarch64_irq, AARCH64_EXC_IRQ_AARCH64)
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VECTOR_FUNC(_lower_el_aarch64_fiq, AARCH64_EXC_FIQ_AARCH64)
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VECTOR_FUNC(_lower_el_aarch64_serror, AARCH64_EXC_SERR_AARCH64)
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VECTOR_FUNC(_lower_el_aarch32_sync, AARCH64_EXC_SYNC_AARCH32)
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VECTOR_FUNC(_lower_el_aarch32_irq, AARCH64_EXC_IRQ_AARCH32)
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VECTOR_FUNC(_lower_el_aarch32_fiq, AARCH64_EXC_FIQ_AARCH32)
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VECTOR_FUNC(_lower_el_aarch32_serror, AARCH64_EXC_SERR_AARCH32)
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@@ -1,31 +1,14 @@
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#include <stdio.h>
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#include <inttypes.h>
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#include "common_aarch64.h"
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#include <lkmc.h>
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#define CNTV_CTL_ENABLE (1 << 0)
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#define CNTV_CTL_IMASK (1 << 1)
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#define CNTV_CTL_ISTATUS (1 << 2)
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/* Frequency in Hz. ? */
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SYSREG_READ_WRITE(uint64_t, cntfrq_el0)
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/* Current virtual counter value. */
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SYSREG_READ(uint64_t, cntvct_el0)
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/* Compare value. See: cntv_ctl_el0_enable. */
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SYSREG_READ_WRITE(uint64_t, cntv_cval_el0)
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/* On write, set cntv_cval_el0 = (cntvct_el0 + cntv_tval_el0).
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* This means that the next interrupt will happen in cntv_tval_el0 cycles.
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*/
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SYSREG_READ_WRITE(uint64_t, cntv_tval_el0)
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/* Control register. */
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SYSREG_READ_WRITE(uint32_t, cntv_ctl_el0)
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void cntv_ctl_el0_disable(void) {
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sysreg_cntv_ctl_el0_write(sysreg_cntv_ctl_el0_read() & ~CNTV_CTL_ENABLE);
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lkmc_sysreg_cntv_ctl_el0_write(lkmc_sysreg_cntv_ctl_el0_read() & ~CNTV_CTL_ENABLE);
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}
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/* If enabled, when: cntv_ctl > cntv_cval then:
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@@ -34,25 +17,25 @@ void cntv_ctl_el0_disable(void) {
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* * set CNTV_CTL_ISTATUS
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*/
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void cntv_ctl_el0_enable(void) {
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sysreg_cntv_ctl_el0_write(sysreg_cntv_ctl_el0_read() | CNTV_CTL_ENABLE);
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lkmc_sysreg_cntv_ctl_el0_write(lkmc_sysreg_cntv_ctl_el0_read() | CNTV_CTL_ENABLE);
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}
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int main(void) {
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/* Initial state. */
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printf("cntv_ctl_el0 0x%" PRIx32 "\n", sysreg_cntv_ctl_el0_read());
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printf("cntfrq_el0 0x%" PRIx64 "\n", sysreg_cntfrq_el0_read());
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printf("cntv_cval_el0 0x%" PRIx64 "\n", sysreg_cntv_cval_el0_read());
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printf("cntv_ctl_el0 0x%" PRIx32 "\n", lkmc_sysreg_cntv_ctl_el0_read());
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printf("cntfrq_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntfrq_el0_read());
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printf("cntv_cval_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntv_cval_el0_read());
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/* Get the counter value many times to watch the time pass. */
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", sysreg_cntvct_el0_read());
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", sysreg_cntvct_el0_read());
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", sysreg_cntvct_el0_read());
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntvct_el0_read());
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntvct_el0_read());
|
||||
printf("cntvct_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntvct_el0_read());
|
||||
|
||||
#if 0
|
||||
/* TODO crashes gem5. */
|
||||
puts("cntfrq_el0 = 1");
|
||||
sysreg_cntfrq_el0_write(1);
|
||||
printf("cntfrq_el0 0x%" PRIx64 "\n", sysreg_cntfrq_el0_read());
|
||||
lkmc_sysreg_cntfrq_el0_write(1);
|
||||
printf("cntfrq_el0 0x%" PRIx64 "\n", lkmc_sysreg_cntfrq_el0_read());
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
Reference in New Issue
Block a user