timing request link

This commit is contained in:
Ciro Santilli 六四事件 法轮功
2020-08-04 02:00:01 +00:00
parent 21e214ccdd
commit e3585078ec

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@@ -13841,7 +13841,7 @@ and their selection can be seen under: `src/dev/arm/RealView.py`, e.g.:
You can place this <<gem5-python-c-interaction,SimObject>> in between two <<gem5-port-system,ports>> to get extra statistics about the packets that are going through. You can place this <<gem5-python-c-interaction,SimObject>> in between two <<gem5-port-system,ports>> to get extra statistics about the packets that are going through.
It only works on timing CPUs, and does not seem to dump any memory values, only add extra <<gem5-m5out-stats-txt-file,statistics>>. It only works on <<gem5-functional-vs-atomic-vs-timing-memory-requests,timing requests>>, and does not seem to dump any memory values, only add extra <<gem5-m5out-stats-txt-file,statistics>>.
For example, the patch link:patches/manual/gem5-commmonitor-se.patch[] hack a `CommMonitor` between the CPU and the L1 cache on top of gem5 1c3662c9557c85f0d25490dc4fbde3f8ab0cb350: For example, the patch link:patches/manual/gem5-commmonitor-se.patch[] hack a `CommMonitor` between the CPU and the L1 cache on top of gem5 1c3662c9557c85f0d25490dc4fbde3f8ab0cb350: