diff --git a/index.html b/index.html
index 0a1afb5..ec8a597 100644
--- a/index.html
+++ b/index.html
@@ -1213,7 +1213,7 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
19.16.2. gem5 ARM RSK
@@ -2925,6 +2925,9 @@ j = 0
the actual command nicely, indented and with arguments broken one per line, but with continuing backslashes so you can just copy paste into a terminal
+
+
For setups that don’t support the newline e.g. Eclipse debugging, you can turn them off with --print-cmd-oneline
+
;: both a valid part of the Bash command, and a visual mark the end of the command
@@ -8287,7 +8290,7 @@ pid=100
-
We choose DerivO3CPU because of the se.py assert:
+
We choose DerivO3CPU because of the se.py assert:
@@ -21461,7 +21464,7 @@ class SystemXBar(CoherentXBar):
BaseKvmCPU
-BaseSimpleCPU
+BaseSimpleCPU: gem5 BaseSimpleCPU
-
@@ -21474,7 +21477,7 @@ class SystemXBar(CoherentXBar):
-MinorO3CPU
+MinorO3CPU: gem5 MinorCPU
BaseO3CPU
@@ -21482,6 +21485,10 @@ class SystemXBar(CoherentXBar):
-
FullO3CPU
+
@@ -21491,6 +21498,12 @@ class SystemXBar(CoherentXBar):
+
+
+
+
+
From this we see that there are basically only 4 C++ CPU models in gem5: Atomic, Timing, Minor and O3. All others are basically parametrizations of those base types.
+
@@ -21590,20 +21603,11 @@ class SystemXBar(CoherentXBar):
Implemented by Pierre-Yves Péneau from LIRMM, which is a research lab in Montpellier, France, in 2017.
-
-O3_ARM_v7a: implemented by Ronald Dreslinski from the University of Michigan in 2012
-
-
Not sure why it has v7a in the name, since I believe the CPUs are just the microarchitectural implementation of any ISA, and the v8 hello world did run.
-
-
-
The CLI option is named slightly differently as: --cpu-type O3_ARM_v7a_3.
-
-
-
+
Generic out-of-order core. "O3" Stands for "Out Of Order"!
@@ -21625,6 +21629,15 @@ class SystemXBar(CoherentXBar):
+
+O3_ARM_v7a: implemented by Ronald Dreslinski from the University of Michigan in 2012
+
+
Not sure why it has v7a in the name, since I believe the CPUs are just the microarchitectural implementation of any ISA, and the v8 hello world did run.
+
+
+
The CLI option is named slightly differently as: --cpu-type O3_ARM_v7a_3.
+
+
@@ -21817,7 +21830,15 @@ cd ..
-
To run and GDB step debug the executable, just copy the full command line from the output ./run, and configure it into Eclipse.
+
To run and GDB step debug the executable, just copy the full command line without newlines from your run command (Eclipse does not like newlines for the arguments), e.g.:
+
+
+
+
./run --emulator gem5 --print-cmd-oneline
+
+
+
+
and configure it into Eclipse as usual.
+
@@ -30559,6 +30590,9 @@ child after parent sleep
userland/linux/sched_getcpu.c
+userland/linux/getcpu.c: a wrapper close the the syscall that also returns the current NUMA node
+
+
userland/linux/sched_getcpu_barrier.c: this uses a barrier to ensure that gem5 will run each thread on one separate CPU
@@ -37928,6 +37962,9 @@ tail -n+1 ../linux-kernel-module-cheat-regression/*/gem5-bench-build-*.txt
Ubuntu 19.10, GCC 9.2.1, LKMC 7c6bb29bc89ec3f1056c0680c3f08bd64018a7bc, gem5 d7d9bc240615625141cd6feddbadd392457e49eb (2020-02-18), ./build --arch aarch64 --gem5-worktree master --no-cache: 19m 33s TODO must investigate why it got so much worse.
+
Ubuntu 20.04, GCC 9.3.0, LKMC 6275f70ed8862d8fe4e58ca4524a6994d254be35, gem5 d9cb548d83fa81858599807f54b52e5be35a6b03 (2020-05-06), ./build --arch aarch64 --gem5-worktree master --no-cache: 28m!!! It’s out of control.
+
+
Same but gem5 d7d9bc240615625141cd6feddbadd392457e49eb (2018-06-17) hacked with -Wnoerror: 11m 37s. So there was a huge regression in the last two years! We have to find it out.