From bc72790e813ef0d724d158a45b153d3ef8f93ebe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ciro=20Santilli=20=E5=85=AD=E5=9B=9B=E4=BA=8B=E4=BB=B6=20?=
 =?UTF-8?q?=E6=B3=95=E8=BD=AE=E5=8A=9F?= <ciro.santilli@gmail.com>
Date: Thu, 6 Jun 2019 00:00:01 +0000
Subject: [PATCH] x86 asm: start moving in binary arithmetic instructions

---
 README.adoc                | 16 ++++++++++++++--
 userland/arch/x86_64/dec.S |  9 +++++++++
 userland/arch/x86_64/inc.S |  9 +++++++++
 userland/arch/x86_64/sub.S |  9 +++++++++
 4 files changed, 41 insertions(+), 2 deletions(-)
 create mode 100644 userland/arch/x86_64/dec.S
 create mode 100644 userland/arch/x86_64/inc.S
 create mode 100644 userland/arch/x86_64/sub.S

diff --git a/README.adoc b/README.adoc
index b83fc17..87d1470 100644
--- a/README.adoc
+++ b/README.adoc
@@ -11756,6 +11756,9 @@ The first examples you should look into are:
 ** <<x86-addressing-modes>>
 ** <<arm-addressing-modes>>
 * registers: <<assembly-registers>>
+* SIMD
+** <<x86-simd>>
+** <<arm-simd>>
 
 The add examples in particular:
 
@@ -12320,6 +12323,15 @@ Bibliography:
 * <<intel-manual-1>> 3.7.5 "Specifying an Offset"
 * https://sourceware.org/binutils/docs-2.18/as/i386_002dMemory.html
 
+=== x86 binary arithmetic instructions
+
+<<intel-manual-1>> 5.1.2 "Binary Arithmetic Instructions":
+
+* link:userland/arch/x86_64/add.S[ADD]
+* link:userland/arch/x86_64/dec.S[DEC]
+* link:userland/arch/x86_64/inc.S[INC]
+* link:userland/arch/x86_64/sub.S[SUB]
+
 === x86 SIMD
 
 History:
@@ -12411,12 +12423,12 @@ Userland basics: http://web.archive.org/web/20190606075544/https://software.inte
 Instruction list: http://web.archive.org/web/20190606075330/https://software.intel.com/sites/default/files/managed/a4/60/325383-sdm-vol-2abcd.pdf
 
 [[intel-manual-3]]
-====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 2
+====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 3
 
 Kernel land: http://web.archive.org/web/20190606075534/https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf
 
 [[intel-manual-4]]
-====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 2
+====== Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 4
 
 Model specific extensions: http://web.archive.org/web/20190606075325/https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf
 
diff --git a/userland/arch/x86_64/dec.S b/userland/arch/x86_64/dec.S
new file mode 100644
index 0000000..5d0e277
--- /dev/null
+++ b/userland/arch/x86_64/dec.S
@@ -0,0 +1,9 @@
+/* Decrement: i--. */
+
+#include <lkmc.h>
+
+LKMC_PROLOGUE
+    mov $3, %rax
+    dec %rax
+    LKMC_ASSERT_EQ_32(%rax, $2)
+LKMC_EPILOGUE
diff --git a/userland/arch/x86_64/inc.S b/userland/arch/x86_64/inc.S
new file mode 100644
index 0000000..263ef16
--- /dev/null
+++ b/userland/arch/x86_64/inc.S
@@ -0,0 +1,9 @@
+/* Increment: i++. */
+
+#include <lkmc.h>
+
+LKMC_PROLOGUE
+    mov $2, %eax
+    inc %eax
+    LKMC_ASSERT_EQ_32(%eax, $3)
+LKMC_EPILOGUE
diff --git a/userland/arch/x86_64/sub.S b/userland/arch/x86_64/sub.S
new file mode 100644
index 0000000..16996ca
--- /dev/null
+++ b/userland/arch/x86_64/sub.S
@@ -0,0 +1,9 @@
+/* Subtraction. */
+
+#include <lkmc.h>
+
+LKMC_PROLOGUE
+    mov $3, %rax
+    sub $2, %rax
+    LKMC_ASSERT_EQ(%rax, $1)
+LKMC_EPILOGUE