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gem5: follow most of TimingSimpleCPU
This commit is contained in:
Ciro Santilli 六四事件 法轮功
355
README.adoc
355
README.adoc
@@ -12185,7 +12185,13 @@ Implementations:
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* `AtomicSimpleCPU`: the default one. Memory accesses happen instantaneously. The fastest simulation except for KVM, but not realistic at all.
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+
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Useful to <<gem5-restore-checkpoint-with-a-different-cpu,boot Linux fast and then checkpoint and switch to a more detailed CPU>>.
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* `TimingSimpleCPU`: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`. TODO: application?
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* `TimingSimpleCPU`: memory accesses are realistic, but the CPU has no pipeline. The simulation is faster than detailed models, but slower than `AtomicSimpleCPU`.
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+
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To fully understand `TimingSimpleCPU`, see: <<gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis>>.
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+
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Without caches, the CPU just stalls all the time waiting for memory requests for every advance of the PC or memory read from a instruction!
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+
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Caches do make a difference here of course, and lead to much faster memory return times.
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<<gem5-kvm,KVM CPUs>> are an alternative way of fast forwarding boot when they work.
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@@ -12570,7 +12576,7 @@ if (_status != Idle)
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+
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A new event is scheduled for the current time itself. TODO what is this event?
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Let's study the first event. From GDB, it's stack trace is:
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Let's study the first event. From <<debug-the-emulator,GDB>>, let's break at the point that prints messages: `Trace::OstreamLogger::logMessage()` to see where events are being scheduled from:
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....
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Trace::OstreamLogger::logMessage() at trace.cc:149 0x5555593b3b1e
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@@ -12658,6 +12664,351 @@ new GlobalSimLoopExitEvent(when + simQuantum, message, exit_code, repeat);
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Tested at b4879ae5b0b6644e6836b0881e4da05c64a6550d.
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===== gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis
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<<gem5-basesimplecpu,TimingSimpleCPU>> should be the second simplest CPU to analyze, so let's give it a try:
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....
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./run \
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--arch aarch64 \
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--emulator gem5 \
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--userland userland/arch/aarch64/freestanding/linux/hello.S \
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--trace Event,ExecAll \
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--trace-stdout \
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-- \
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--cpu-type TimingSimpleCPU \
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;
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....
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As of LKMC 9bfbff244d713de40e5686bd370eadb20cf78c7b + 1 the log is now much more complex.
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Here is an abridged version with:
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* the beginning up to the second instruction
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* end ending
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because all that happens in between is exactly the same as the first two instructions and therefore boring:
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....
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0: system.cpu.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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**** REAL SIMULATION ****
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0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 7786250
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0: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped event scheduled @ 7786250
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0: Event_74: generic event scheduled @ 0
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info: Entering event queue @ 0. Starting simulation...
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0: Event_74: generic event rescheduled @ 18446744073709551615
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0: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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0: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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0: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 46250
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0: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 5000
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0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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46250: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 74250
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74250: system.membus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 77000
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74250: system.membus.respLayer1.wrapped_function_event: EventFunctionWrapped event scheduled @ 77000
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77000: Event_40: Timing CPU icache tick event scheduled @ 77000
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77000: system.cpu A0 T0 : @asm_main_after_prologue : movz x0, #1, #0 : IntAlu : D=0x0000000000000001 flags=(IsInteger)
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77000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 77000
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77000: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped event scheduled @ 78000
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77000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 95750
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77000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 77000
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95750: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 123750
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123750: system.membus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 126000
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123750: system.membus.respLayer1.wrapped_function_event: EventFunctionWrapped event scheduled @ 126000
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126000: Event_40: Timing CPU icache tick event scheduled @ 126000
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[...]
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469000: system.cpu A0 T0 : @asm_main_after_prologue+28 : svc #0x0 : IntAlu : flags=(IsSerializeAfter|IsNonSpeculative|IsSyscall)
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469000: Event_75: generic event scheduled @ 469000
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....
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`0: system.cpu.wrapped_function_event` schedule the initial tick, much like for for `AtomicSimpleCPU`. This time however, it is not a tick, but rather a fetch event that gets scheduled:
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....
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TimingSimpleCPU::activateContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
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assert(thread_num < numThreads);
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threadInfo[thread_num]->notIdleFraction = 1;
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if (_status == BaseSimpleCPU::Idle)
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_status = BaseSimpleCPU::Running;
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// kick things off by initiating the fetch of the next instruction
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if (!fetchEvent.scheduled())
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schedule(fetchEvent, clockEdge(Cycles(0)));
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....
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We have a fetch instead of a tick here compared to `AtomicSimpleCPU`, because in the timing CPU we must first get the instruction opcode from DRAM, which takes some cycles to return!
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By looking at the source, we see that fetchEvent runs `TimingSimpleCPU::fetch`.
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`0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 7786250`: from GDB we see that it comes from `DRAMCtrl::startup` in `mem/dram_ctrl.cc` which contains:
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....
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void
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DRAMCtrl::startup()
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{
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// remember the memory system mode of operation
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isTimingMode = system()->isTimingMode();
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if (isTimingMode) {
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// timestamp offset should be in clock cycles for DRAMPower
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timeStampOffset = divCeil(curTick(), tCK);
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// update the start tick for the precharge accounting to the
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// current tick
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for (auto r : ranks) {
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r->startup(curTick() + tREFI - tRP);
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}
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// shift the bus busy time sufficiently far ahead that we never
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// have to worry about negative values when computing the time for
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// the next request, this will add an insignificant bubble at the
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// start of simulation
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nextBurstAt = curTick() + tRP + tRCD;
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}
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}
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....
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which then calls:
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....
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void
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DRAMCtrl::Rank::startup(Tick ref_tick)
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{
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assert(ref_tick > curTick());
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pwrStateTick = curTick();
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// kick off the refresh, and give ourselves enough time to
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// precharge
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schedule(refreshEvent, ref_tick);
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}
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....
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By looking up some variable definitions in the source, we now we see some memory parameters clearly:
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* ranks: `std::vector<DRAMCtrl::Rank*>` with 2 elements. TODO why do we have 2? What does it represent? Likely linked to <<gem5-config-ini,`config.ini`>> at `system.mem_ctrls.ranks_per_channel=2`
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* `tCK=1250`, `tREFI=7800000`, `tRP=13750`, `tRCD=13750`: all defined in a single code location with a comment:
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+
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....
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/**
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* Basic memory timing parameters initialized based on parameter
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* values.
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*/
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....
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+
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Their values can be seen under `config.ini` and they are documented in `src/mem/DRAMCtrl.py` e.g.:
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+
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....
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# the base clock period of the DRAM
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tCK = Param.Latency("Clock period")
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# minimum time between a precharge and subsequent activate
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tRP = Param.Latency("Row precharge time")
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# the amount of time in nanoseconds from issuing an activate command
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# to the data being available in the row buffer for a read/write
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tRCD = Param.Latency("RAS to CAS delay")
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# refresh command interval, how often a "ref" command needs
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# to be sent. It is 7.8 us for a 64ms refresh requirement
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tREFI = Param.Latency("Refresh command interval")
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....
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So we realize that we are going into deep DRAM modelling, more detail that a mere mortal should ever need to know.
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`curTick() + tREFI - tRP = 0 + 7800000 - 13750 = 7786250` which is when that `refreshEvent` was scheduled. Our simulation ends way before that point however, so we will never know what it did thank God.
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`0: Event_74: generic event scheduled @ 0` and `0: Event_74: generic event rescheduled @ 18446744073709551615`: schedule the final exit event, same as for `AtomicSimpleCPU`
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The next interesting event is:
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....
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system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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....
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which comes from:
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....
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#0 Trace::OstreamLogger::logMessage
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#1 void Trace::Logger::dprintf
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#2 Event::trace
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#3 EventQueue::schedule
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#4 EventManager::schedule
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#5 DRAMCtrl::addToReadQueue
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#6 DRAMCtrl::recvTimingReq
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#7 DRAMCtrl::MemoryPort::recvTimingReq
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#8 TimingRequestProtocol::sendReq
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#9 MasterPort::sendTimingReq
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#10 CoherentXBar::recvTimingReq
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#11 CoherentXBar::CoherentXBarSlavePort::recvTimingReq(Packet*))
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#12 TimingRequestProtocol::sendReq
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#13 MasterPort::sendTimingReq
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#14 TimingSimpleCPU::sendFetch
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#15 TimingSimpleCPU::FetchTranslation::finish
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#16 ArmISA::TLB::translateComplete
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#17 ArmISA::TLB::translateTiming
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#18 ArmISA::TLB::translateTiming
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#19 TimingSimpleCPU::fetch
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#20 TimingSimpleCPU::<lambda()>::operator()(void)
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#21 std::_Function_handler<void(), TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams*)::<lambda()> >
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#22 std::function<void)>::operator()() const
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#23 EventFunctionWrapper::process
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#24 EventQueue::serviceOne
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#25 doSimLoop
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#26 simulate
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....
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From the trace, we see that we are already running from the event queue. Therefore, we must have been running a previously scheduled event, and the previous event logs, the only such event is `0: system.cpu.wrapped_function_event: EventFunctionWrapped event scheduled @ 0` which scheduled a memory fetch!
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From the backtrace we see the tortuous path that the data request takes, going through:
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* `ArmISA::TLB`
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* `CoherentXBar`
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* `DRAMCtrl`
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The scheduling happens at frame `#5`:
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....
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// If we are not already scheduled to get a request out of the
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// queue, do so now
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if (!nextReqEvent.scheduled()) {
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DPRINTF(DRAM, "Request scheduled immediately\n");
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schedule(nextReqEvent, curTick());
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}
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....
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and from a quick source grep we see that `nextReqEvent` is a `DRAMCtrl::processNextReqEvent`.
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The next schedule:
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....
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0: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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....
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and does a `BaseXBar::Layer::releaseLayer` event.
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This one is also coming from the request queue at `TimingSimpleCPU::fetch`. We deduce therefore that the single previous fetch event scheduled not one, but two events!
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Now:
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....
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0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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....
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comes from the previously scheduled `DRAMCtrl::processNextReqEvent` and schedules `DRAMCtrl::Rank::processPrechargeEvent`.
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Now:
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....
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0: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 46250
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....
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also runs from `DRAMCtrl::processNextReqEvent` and schedules a `DRAMCtrl::processRespondEvent`.
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I'm getting bored, let's skip to the line that appears to matter for the first instruction:
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....
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46250: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 74250
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....
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But I got even more bored, and I will now skip to the first event before the instruction:
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....
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77000: Event_40: Timing CPU icache tick event scheduled @ 77000
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77000: system.cpu A0 T0 : @asm_main_after_prologue : movz x0, #1, #0 : IntAlu : D=0x0000000000000001 flags=(IsInteger)
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....
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This event comes from `PacketQueue::processSendEvent` and schedules itself:
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....
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void
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TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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{
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pkt = _pkt;
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cpu->schedule(this, t);
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}
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....
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which polymorphically resolves to:
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....
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void
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TimingSimpleCPU::IcachePort::ITickEvent::process()
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{
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cpu->completeIfetch(pkt);
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}
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....
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and so `TimingSimpleCPU::completeIfetch` is, at last, the interesting `TimingSimpleCPU` function!
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The end of this instruction must be setting things up in a way that can continue the PC walk loop, and by looking at the source and traces, it is clearly from: `TimingSimpleCPU::advanceInst` which calls `TimingSimpleCPU::fetch`, which is the very thing we did in this simulation!!! OMG, that's the loop.
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One final thing to check, is how the memory reads are going to make the processor stall in the middle of an instruction.
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For that, we can GDB to the `TimingSimpleCPU::completeIfetch` of the first LDR done in our test program.
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By doing that, we see that this time at:
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....
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if (curStaticInst && curStaticInst->isMemRef()) {
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// load or store: just send to dcache
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Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
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if (_status == BaseSimpleCPU::Running) {
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}
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} else if (curStaticInst) {
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// non-memory instruction: execute completely now
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Fault fault = curStaticInst->execute(&t_info, traceData);
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....
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* `curStaticInst->isMemRef()` is true, and there is no instruction `execute` call in that part of the branch, only for instructions that don't touch memory
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* `_status` is `BaseSimpleCPU::Status::DcacheWaitResponse` and `advanceInst` is not yet called
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So, where is the `execute` happening? Well, I'll satisfy myself with a quick source grep and guess:
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* `curStaticInst->initiateAcc` sets up some memory request events
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* which likely lead up to: `TimingSimpleCPU::completeDataAccess`, which off the bat ends in `advanceInst`.
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+
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It also calls `curStaticInst->completeAcc`, which pairs up with the `initiateAcc` call.
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===== gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches
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Let's just add --caches to see if things go any faster:
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....
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0: system.cpu.wrapped_function_event: EventFunctionWrapped event scheduled @ 0
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**** REAL SIMULATION ****
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0: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 7786250
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0: system.mem_ctrls_1.wrapped_function_event: EventFunctionWrapped event scheduled @ 7786250
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0: Event_84: generic event scheduled @ 0
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info: Entering event queue @ 0. Starting simulation...
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0: Event_84: generic event rescheduled @ 18446744073709551615
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0: system.cpu.icache.mem_side-MemSidePort.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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1000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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1000: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped event scheduled @ 2000
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1000: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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1000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 46250
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1000: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped event scheduled @ 5000
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1000: system.mem_ctrls_0.wrapped_function_event: EventFunctionWrapped event scheduled @ 1000
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46250: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 74250
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74250: system.membus.slave[1]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped event scheduled @ 77000
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74250: system.membus.respLayer1.wrapped_function_event: EventFunctionWrapped event scheduled @ 80000
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77000: system.cpu.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped event scheduled @ 78000
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78000: Event_40: Timing CPU icache tick event scheduled @ 78000
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78000: system.cpu A0 T0 : @asm_main_after_prologue : movz x0, #1, #0 : IntAlu : D=0x0000000000000001 flags=(IsInteger)
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78000: system.cpu.icache.cpu_side-CpuSidePort.wrapped_function_event: EventFunctionWrapped event scheduled @ 83000
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83000: Event_40: Timing CPU icache tick event scheduled @ 83000
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83000: system.cpu A0 T0 : @asm_main_after_prologue+4 : adr x1, #28 : IntAlu : D=0x0000000000400098 flags=(IsInteger)
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[...]
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191000: system.cpu A0 T0 : @asm_main_after_prologue+28 : svc #0x0 : IntAlu : flags=(IsSerializeAfter|IsNonSpeculative|IsSyscall)
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191000: Event_85: generic event scheduled @ 191000
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....
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So yes, `--caches` does work here, leading to a runtime of 191000 rather than 469000 without caches!
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===== gem5 event queue MinorCPU syscall emulation freestanding example analysis
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The events <<gem5-event-queue-atomicsimplecpu-syscall-emulation-freestanding-example-analysis,for the Atomic CPU>> were pretty simple: basically just ticks.
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