mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-23 02:05:57 +01:00
baremetal: all examples working, all failures accounted for!
SIMD&FP is now enabled in arm from bootloader.
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@@ -2,15 +2,15 @@
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.global lkmc_start
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lkmc_start:
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/* = NEON setup */
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mov x1, #(0x3 << 20)
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msr cpacr_el1, x1
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isb
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/* Load the vector table. */
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ldr x0, =lkmc_vector_table
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msr vbar_el1, x0
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/* https://github.com/cirosantilli/linux-kernel-module-cheat#aarch64-baremetal-neon-setup */
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mov x1, 0x3 << 20
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msr cpacr_el1, x1
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isb
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/* Prepare the stack for main, mandatory for C code. */
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ldr x0, =stack_top
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mov sp, x0
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@@ -30,8 +30,8 @@ LKMC_VECTOR_TABLE
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/* Default trap handler. */
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LKMC_WEAK(lkmc_vector_trap_handler)
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ldr x0, =lkmc_vector_trap_handler_error
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ldr x0, =lkmc_vector_trap_handler_error_message
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bl puts
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bl abort
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lkmc_vector_trap_handler_error:
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lkmc_vector_trap_handler_error_message:
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.asciz "error: unexpected interrupt"
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@@ -5,6 +5,19 @@ lkmc_start:
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/* Prepare the stack for main, mandatory for C code. */
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ldr sp, =stack_top
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/* Enable floating point.
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* Code copied from: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0409h/CHDEGGFF.html
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* Without this, SIMD operations such as vmov raise an exception.
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*/
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mrc p15, 0, r0, c1, c0, 2 /* Read CPACR into r0 */
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orr r0, r0, 3 << 20 /* OR in User and Privileged access for CP10 */
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orr r0, r0, 3 << 22 /* OR in User and Privileged access for CP11 */
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bic r0, r0, 3 << 30 /* Clear ASEDIS/D32DIS if set */
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mcr p15, 0, r0, c1, c0, 2 /* Store new access permissions into CPACR */
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isb /* Ensure side-effect of CPACR is visible */
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mov r0, 1 << 30 /* Create value with FPEXC (bit 30) set in r0 */
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vmsr fpexc, r0 /* Enable VFP and SIMD extensions */
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/* https://github.com/cirosantilli/linux-kernel-module-cheat#magic-failure-string */
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ldr r0, =lkmc_baremetal_on_exit_callback
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bl on_exit
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