aarch64: fix bus error on aarch64 in ThunderX2 misaligned PC

The error happened at: userland/arch/aarch64/lkmc_assert_eq_fail.S but
it does not happen in QEMU userland nor full system, not sure why.

README.adoc

@@ -12517,6 +12517,20 @@ Some random ones:
 
 * aarch32 has two encodings: Thumb and ARM: <<arm-instruction-encodings>>
 * in ARMv8, the stack has to 16-byte aligned. Therefore, the main way to push things to stack is with 8-byte pair pushes with the <<armv8-aarch64-ldp-and-stp-instructions>>
++
+<<armarm8-db>> C1.3.3 "Load/Store addressing modes" says:
++
+____
+When stack alignment checking is enabled by system software and the base register is the SP, the current stack pointer must be initially quadword aligned, that is aligned to 16 bytes. Misalignment generates a Stack Alignment fault. The offset does not have to be a multiple of 16 bytes unless the specific Load/Store instruction requires this. SP cannot be used as a register offset.
+____
++
+<<armarm8-db>> C3.2 "Loads and stores" says:
++
+____
+The additional control bits SCTLR_ELx.SA and SCTLR_EL1.SA0 control whether the stack pointer must be quadword aligned when used as a base register. See SP alignment checking on page D1-2164. Using a misaligned stack pointer generates an SP alignment fault exception.
+____
++
+<<armarm8-db>> D1.8.2 "SP alignment checking" is then the main section.
 
 ==== Free ARM implementations
 
@@ -12768,6 +12782,8 @@ Bibliography: <<armarm7>>:
 * A4.6.5 "Addressing modes"
 * A8.5 "Memory accesses"
 
+<<armarm8>>: C1.3.3 "Load/Store addressing modes"
+
 ====== ARM loop over array
 
 As an application of the post-indexed addressing mode, let's increment an array.
@@ -14042,6 +14058,10 @@ Bibliography: https://stackoverflow.com/questions/20055754/arm-start-wakeup-brin
 
 TODO: create and study a minimal examples in gem5 where the DMB instruction leads to less cycles: https://stackoverflow.com/questions/15491751/real-life-use-cases-of-barriers-dsb-dmb-isb-in-arm
 
+==== ARM timer
+
+TODO get working. Attempt at: link:baremetal/arch/aarch64/timer.c[]
+
 ==== ARM baremetal bibliography
 
 First, also consider the userland bibliography: <<arm-assembly-bibliography>>.

lkmc/aarch64.h

@@ -17,9 +17,9 @@
 ;
 
 #define LKMC_ASSERT_EQ_REG_32(reg1, reg2) \
-    str reg2, [sp, -4]!; \
+    str reg2, [sp, -16]!; \
     mov w0, reg1; \
-    ldr w1, [sp], 4; \
+    ldr w1, [sp], 16; \
     ldr w2, =__LINE__; \
     bl lkmc_assert_eq_32; \
 ;