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ld2 move in

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Ciro Santilli 六四事件 法轮功
2019-05-12 00:00:10 +00:00
parent 11359838a1
commit 9f9db3680d
2 changed files with 28 additions and 20 deletions
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46
README.adoc
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@@ -12606,7 +12606,25 @@ Bibliography: https://stackoverflow.com/questions/1875491/nop-for-iphone-binarie
=== ARM SIMD === ARM SIMD
==== ARM fadd vs vadd ==== ARM vadd instruction
link:userland/arch/arm/vadd.S[]
Good first instruction to learn SIMD: <<simd-assembly>>
==== ARMv8 aarch64 add vector instruction
link:userland/arch/aarch64/add_vector.S[]
Good first instruction to learn SIMD: <<simd-assembly>>
==== ARMv8 aarch64 fadd vector instruction
link:userland/arch/aarch64/fadd_vector.S[]
Good first instruction to learn SIMD: <<simd-assembly>>
===== ARM fadd vs vadd
It is very confusing, but `fadds` and `faddd` in Aarch32 are <<gnu-gas-assembler-arm-unified-syntax,pre-UAL>> for `vadd.f32` and `vadd.f64` which we use in this tutorial: <<arm-vadd-instruction>> It is very confusing, but `fadds` and `faddd` in Aarch32 are <<gnu-gas-assembler-arm-unified-syntax,pre-UAL>> for `vadd.f32` and `vadd.f64` which we use in this tutorial: <<arm-vadd-instruction>>
@@ -12618,27 +12636,17 @@ Also keep in mind that fused multiply add is `fmadd`.
Examples at: <<simd-assembly>> Examples at: <<simd-assembly>>
==== ARM SIMD instructions ==== arm ld2 instruction
===== ARM vadd instruction Example: link:userland/arch/aarch64/ld2.S[]
link:userland/arch/arm/vadd.S[] We can load multiple vectors interleaved from memory in one single instruction!
Good first instruction to learn SIMD: <<simd-assembly>> This is why the `ldN` instructions take an argument list denoted by `{}` for the registers, much like armv7 <<ldmia>>.
===== ARMv8 aarch64 add vector instruction There are analogous `ld3` and `ld4` instruction.
link:userland/arch/aarch64/add_vector.S[] ==== ARM vcvt instruction
Good first instruction to learn SIMD: <<simd-assembly>>
===== ARMv8 aarch64 fadd vector instruction
link:userland/arch/aarch64/fadd_vector.S[]
Good first instruction to learn SIMD: <<simd-assembly>>
===== ARM vcvt instruction
Example: link:userland/arch/arm/vcvt.S[] Example: link:userland/arch/arm/vcvt.S[]
@@ -12658,7 +12666,7 @@ E.g., in our 32-bit float to 32-bit unsigned example we use:
vld1.32.f32 vld1.32.f32
.... ....
====== ARM vcvtr instruction ===== ARM vcvtr instruction
Example: link:userland/arch/arm/vcvtr.S[] Example: link:userland/arch/arm/vcvtr.S[]
@@ -12670,7 +12678,7 @@ Rounding mode selection is exposed in the ANSI C standard through link:https://e
TODO: is the initial rounding mode specified by the ELF standard? Could not find a reference. TODO: is the initial rounding mode specified by the ELF standard? Could not find a reference.
====== ARM vcvta instruction ===== ARM vcvta instruction
Example: link:userland/arch/arm/vcvt.S[] Example: link:userland/arch/arm/vcvt.S[]

2
userland/arch/aarch64/simd_interleave.S → userland/arch/aarch64/ld2.S
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@@ -1,4 +1,4 @@
/* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-simd-interleaving */ /* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-ld2-instruction */
#include "common.h" #include "common.h"