mirror of
https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-27 20:14:27 +01:00
Make userland / assembly getting started more uniform / visible
Forward --gcc-which to ./run --tmux. Use gdb-multiarch for --gcc-which host.
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@@ -3,16 +3,6 @@
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#include "common.h"
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.data;
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a1:
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.float 0.0, 0.5, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5
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a2:
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.float 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5
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sum:
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.skip 32
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sum_expect:
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.float 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0
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ENTRY
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/* Minimal single precision floating point example.
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* TODO: floating point representation constraints due to 4-byte instruction?
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@@ -79,74 +69,4 @@ my_float_sum:
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vmov s1, s0
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vmov r1, s1
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ASSERT_EQ_REG(r0, r1)
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/* Now a more complex test function. */
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ldr r0, =sum
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ldr r1, =a1
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ldr r2, =a2
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mov r3, 8
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bl vec_sum
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/* The assert works easily because all floats used
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* have exact base-2 representation.
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*/
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ASSERT_MEMCMP(sum, sum_expect, 0x20)
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EXIT
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/* void vec_sum(float *sum, float *a1, float *a2, int length) {
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* int i;
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* for (i=0; i < length; i++)
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* *(sum+i) = *(a1+i) + *(a2+i);
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* }
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*/
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vec_sum:
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/* Setup */
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push {r0, r1, r4, lr}
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push {r0, r1}
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mov r0, 1
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mov r1, 8
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bl reconfig
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pop {r0, r1}
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asr r3, 3
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/* Do the sum. */
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1:
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fldmias r1!, {s8-s15}
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fldmias r2!, {s16-s23}
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vadd.f32 s24, s8, s16
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fstmias r0!, {s24-s31}
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subs r3, r3, 1
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bne 1b
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/* Teardown. */
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bl deconfig
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pop {r0, r1, r4, pc}
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/* inputs:
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* r0: desired vector stride (1 or 2)
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* r1: desired vector length (min. 1, max. 8)
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* outputs: (none)
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* modified: r0, r1, FPSCR
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* notes:
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* r0 and r1 will be truncated before fitting into FPSCR
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*/
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reconfig:
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push {r0-r2}
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and r0, r0, 3
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eor r0, r0, 1
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sub r1, r1, 1
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and r1, r1, 7
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mov r0, r0, lsl 20
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orr r0, r0, r1, lsl 16
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vmrs r2, fpscr
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bic r2, 55*65536
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orr r2, r2, r0
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vmsr fpscr, r0
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pop {r0-r2}
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bx lr
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deconfig:
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push {r0, r1, lr}
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mov r0, 1
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mov r1, 1
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bl reconfig
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pop {r0, r1, pc}
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