3rd-party/linux-kernel-module-cheat
1
0
Fork 0
mirror of https://github.com/cirosantilli/linux-kernel-module-cheat.git synced 2026-01-23 02:05:57 +01:00
Code Issues Releases Wiki Activity

baremetal aarch64: timer.c get closer to working

Browse Source
This commit is contained in:
Ciro Santilli 六四事件 法轮功
2019-06-16 00:00:02 +00:00
parent b3874cc72b
commit 89084d2332
5 changed files with 60 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
README.adoc
View File

@@ -14156,6 +14156,15 @@ TODO: create and study a minimal examples in gem5 where the DMB instruction lead
TODO get working. Attempt at: link:baremetal/arch/aarch64/timer.c[]
The timer is documented at: <<armarm8-db>> Chapter D10 "The Generic Timer in AArch64 state"
The key registers to keep in mind are:
* `CNTVCT_EL0`: "Counter-timer Virtual Count register". The increasing current counter value.
* `CNTFRQ_EL0`: "Counter-timer Frequency register". "Indicates the system counter clock frequency, in Hz."
* `CNTV_CTL_EL0`: "Counter-timer Virtual Timer Control register"
* `CNTV_CVAL_EL0`: "Counter-timer Virtual Timer CompareValue register". The interrupt happens when `CNTVCT_EL0` reaches the value in this register.
==== ARM baremetal bibliography
First, also consider the userland bibliography: <<arm-assembly-bibliography>>.
@@ -14208,7 +14217,7 @@ which further confirms that the exception is correct: v2 has a register range at
The original source does not mention GICv3 anywhere, only link:https://github.com/takeharukato/sample-tsk-sw/blob/c7bbc9dce6b14660bcce8d20735f8c6ebb09396b/hal/aarch64/gic-pl390.c[pl390], which is a specific GIC model that predates the GICv2 spec I believe.
TODO I hacked `#define GIC_GICC_BASE (GIC_BASE + 0xa0000)` and now continuing attempt.
TODO if I hack `#define GIC_GICC_BASE (GIC_BASE + 0xa0000)`, then it goes a bit further, but the next loop never ends.
===== tukl-msd/gem5.bare-metal