arm sve: enable on baremetal by setting missing bits CPACR_EL1.ZEN

This commit is contained in:
Ciro Santilli 六四事件 法轮功
2019-07-25 00:00:00 +00:00
parent 1f75ce8f12
commit 87e846fc1f
4 changed files with 43 additions and 9 deletions

View File

@@ -4,22 +4,22 @@
LKMC_PROLOGUE
/* 0x00 && 0xFF == 0x00 */
/* 0x00 & 0xFF == 0x00 */
mov r0, 0x00
and r0, 0xFF
LKMC_ASSERT_EQ(r0, =0x00)
/* 0x0F && 0xF0 == 0x00 */
/* 0x0F & 0xF0 == 0x00 */
mov r0, 0x0F
and r0, 0xF0
LKMC_ASSERT_EQ(r0, =0x00)
/* 0x0F && 0xFF == 0x0F */
/* 0x0F & 0xFF == 0x0F */
mov r0, 0x0F
and r0, 0xFF
LKMC_ASSERT_EQ(r0, =0x0F)
/* 0xF0 && 0xFF == 0xF0 */
/* 0xF0 & 0xFF == 0xF0 */
mov r0, 0xF0
and r0, 0xFF
LKMC_ASSERT_EQ(r0, =0xF0)

27
userland/arch/arm/orr.S Normal file
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@@ -0,0 +1,27 @@
/* https://cirosantilli.com/linux-kernel-module-cheat#arm-bitwise-instructions */
#include <lkmc.h>
LKMC_PROLOGUE
/* 0x00 | 0xFF == 0x00 */
mov r0, 0x00
orr r0, 0xFF
LKMC_ASSERT_EQ(r0, =0xFF)
/* 0x0F | 0xF0 == 0x00 */
mov r0, 0x0F
orr r0, 0xF0
LKMC_ASSERT_EQ(r0, =0xFF)
/* 0x0F | 0x0F == 0x0F */
mov r0, 0x0F
orr r0, 0x0F
LKMC_ASSERT_EQ(r0, =0x0F)
/* 0xF0 | 0xF0 == 0xF0 */
mov r0, 0xF0
and r0, 0xF0
LKMC_ASSERT_EQ(r0, =0xF0)
LKMC_EPILOGUE