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readme: fix some c++ -> that expands to crazy char
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@@ -13043,15 +13043,15 @@ if (curStaticInst && curStaticInst->isMemRef()) {
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Fault fault = curStaticInst->execute(&t_info, traceData);
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Fault fault = curStaticInst->execute(&t_info, traceData);
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....
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....
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* `curStaticInst->isMemRef()` is true, and there is no instruction `execute` call in that part of the branch, only for instructions that don't touch memory
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* `+curStaticInst->isMemRef()+` is true, and there is no instruction `execute` call in that part of the branch, only for instructions that don't touch memory
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* `_status` is `BaseSimpleCPU::Status::DcacheWaitResponse` and `advanceInst` is not yet called
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* `_status` is `BaseSimpleCPU::Status::DcacheWaitResponse` and `advanceInst` is not yet called
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So, where is the `execute` happening? Well, I'll satisfy myself with a quick source grep and guess:
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So, where is the `execute` happening? Well, I'll satisfy myself with a quick source grep and guess:
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* `curStaticInst->initiateAcc` sets up some memory request events
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* `+curStaticInst->initiateAcc+` sets up some memory request events
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* which likely lead up to: `TimingSimpleCPU::completeDataAccess`, which off the bat ends in `advanceInst`.
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* which likely lead up to: `TimingSimpleCPU::completeDataAccess`, which off the bat ends in `advanceInst`.
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+
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+
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It also calls `curStaticInst->completeAcc`, which pairs up with the `initiateAcc` call.
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It also calls `+curStaticInst->completeAcc+`, which pairs up with the `initiateAcc` call.
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===== gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches
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===== gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches
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