From 6dfc95d73aeb5975849819215013da79cc9b9e86 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ciro=20Santilli=20=E5=85=AD=E5=9B=9B=E4=BA=8B=E4=BB=B6=20?=
 =?UTF-8?q?=E6=B3=95=E8=BD=AE=E5=8A=9F?= <ciro.santilli@gmail.com>
Date: Sun, 25 Aug 2019 00:00:00 +0000
Subject: [PATCH] arm: signed LDR example with LDRSW

---
 README.adoc                   |  4 ++++
 userland/arch/aarch64/ldrsw.S | 30 ++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 userland/arch/aarch64/ldrsw.S

diff --git a/README.adoc b/README.adoc
index 3f1cdad..55db2bf 100644
--- a/README.adoc
+++ b/README.adoc
@@ -14696,6 +14696,10 @@ There are LDR variants that load less than full 4 bytes:
 * link:userland/arch/arm/ldrb.S[]: load byte
 * link:userland/arch/arm/ldrh.S[]: load half word
 
+These also have signed and unsigned versions to either zero or one extend the result:
+
+* link:userland/arch/aarch64/ldrsw.S[]: load byte and sign extend
+
 ==== ARM STR instruction
 
 Store from memory into registers.
diff --git a/userland/arch/aarch64/ldrsw.S b/userland/arch/aarch64/ldrsw.S
new file mode 100644
index 0000000..13cc051
--- /dev/null
+++ b/userland/arch/aarch64/ldrsw.S
@@ -0,0 +1,30 @@
+/* https://cirosantilli.com/linux-kernel-module-cheat#arm-ldrh-and-ldrb-instructions */
+
+#include <lkmc.h>
+
+LKMC_PROLOGUE
+    ldr x19, =zero_extend
+
+    mov x0, 0x0
+    ldr w0, [x19]
+    LKMC_ASSERT_EQ(x0, =0x0000000012345678)
+
+    mov x0, 0x0
+    ldrsw x0, [x19]
+    LKMC_ASSERT_EQ(x0, =0x0000000012345678)
+
+    ldr x19, =one_extend
+
+    mov x0, 0x0
+    ldr w0, [x19]
+    LKMC_ASSERT_EQ(x0, =0x0000000082345678)
+
+    mov x0, 0x0
+    ldrsw x0, [x19]
+    LKMC_ASSERT_EQ(x0, =0xFFFFFFFF82345678)
+
+LKMC_EPILOGUE
+zero_extend:
+    .word 0x12345678
+one_extend:
+    .word 0x82345678