diff --git a/README.adoc b/README.adoc
index be3138d..325de64 100644
--- a/README.adoc
+++ b/README.adoc
@@ -16622,6 +16622,8 @@ cntv_cval_el0 0xB439642
 
 and new `IRQ number` section appears every second, when a clock interrupt is raised!
 
+TODO make work on gem5. Fails with <<gem5-simulate-limit-reached>> at the first WFI done in main, which means that the interrupt is never raised.
+
 Once an interrupt is raised, the interrupt itself sets up a new interrupt to happen in one second in the future after `cntv_cval_el0` is reached by the counter.
 
 The timer is part of the aarch64 specification itself and is documented at: <<armarm8-db>> Chapter D10 "The Generic Timer in AArch64 state". The key registers to keep in mind are:
diff --git a/baremetal/arch/aarch64/timer.c b/baremetal/arch/aarch64/timer.c
index d658659..d094e5e 100644
--- a/baremetal/arch/aarch64/timer.c
+++ b/baremetal/arch/aarch64/timer.c
@@ -102,22 +102,9 @@ int main(void) {
     lkmc_sysreg_print_cntvct_el0();
     puts("");
 
-<<<<<<< Updated upstream
-    gic_v3_initialize();
-    {
-        /*uint64_t ticks, current_cnt;*/
-        /*uint32_t cntfrq;*/
-        /*ticks = cntfrq;*/
-        /*current_cnt = lkmc_sysreg_read_cntvct_el0();*/
-        /*lkmc_sysreg_write_cntv_cval_el0(current_cnt + ticks);*/
-        enable_cntv();
-        enable_irq();
-    }
-=======
     gic_initialize();
     enable_cntv();
     enable_irq();
->>>>>>> Stashed changes
     while (1) {
         lkmc_arm_aarch64_wfi();
     }
diff --git a/lkmc/gic.h b/lkmc/gic.h
index dd5bd8b..c92b978 100644
--- a/lkmc/gic.h
+++ b/lkmc/gic.h
@@ -4,14 +4,36 @@
 #include <lkmc/aarch64.h>
 
 #if LKMC_QEMU
+
 /* info qtree contains:
+ *
  *   dev: arm_gic, id ""
- *     mmio 0000000008000000/0000000000001000 */
-#define GIC_BASE       0x08000000
+ *    mmio 0000000008000000/0000000000001000
+ *    mmio 0000000008010000/0000000000002000 */
+#define GIC_GICD_BASE 0x08000000
+#define GIC_GICC_BASE 0x08010000
+#define TIMER_IRQ     27
+
 #elif LKMC_GEM5
-/* https://github.com/gem5/gem5/blob/f525028c126af33da532f6703a152d81d900dcf7/src/dev/arm/RealView.py#L952 */
-#define GIC_BASE       0x2c001000
+
+/* On source at: https://github.com/gem5/gem5/blob/f525028c126af33da532f6703a152d81d900dcf7/src/dev/arm/RealView.py#L952
+ *
+ * On m5out/config.ini at:
+ *
+ * * system.realview.gic.dist_addr=738201600
+ * * system.realview.gic.cpu_addr=738205696
+ *
+ * On auto-generated DTB in m5out/system.dtb after converstion to dts:
+ *
+ * interrupt-controller {
+ *       compatible = "gem5,gic", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ *       reg = <0x0 0x2c001000 0x0 0x1000 0x0 0x2c002000 0x0 0x1000 0x0 0x2c004000 0x0 0x2000 0x0 0x2c006000 0x0 0x2000>; * */
+#define GIC_GICD_BASE 0x2c001000
+#define GIC_GICC_BASE 0x2c002000
+#define TIMER_IRQ     30
+
 #endif
+
 #define GIC_INT_MAX    64
 #define GIC_PRIO_MAX   16
 #define GIC_INTNO_SGI0 0
@@ -19,13 +41,9 @@
 #define GIC_INTNO_SPI0 32
 #define GIC_PRI_SHIFT  4
 #define GIC_PRI_MASK   0x0f
-#define TIMER_IRQ      27
 
 typedef int32_t irq_no;
 
-#define GIC_GICD_BASE (GIC_BASE)
-#define GIC_GICC_BASE (GIC_BASE + 0x10000)
-
 #define GIC_GICD_INT_PER_REG            (32)
 #define GIC_GICD_IPRIORITY_PER_REG      (4)
 #define GIC_GICD_IPRIORITY_SIZE_PER_REG (8)