multicore: remove references to PCSI

README.adoc

@@ -10603,10 +10603,7 @@ since gem5 is able to detect when nothing will ever happen, and exits.
 
 When GDB step debugging, switch between cores with the usual `thread` commands, see also: <<gdb-step-debug-multicore-userland>>.
 
-Bibliography:
-
-* https://stackoverflow.com/questions/20055754/arm-start-wakeup-bringup-the-other-cpu-cores-aps-and-pass-execution-start-addre
-* https://stackoverflow.com/questions/980999/what-does-multicore-assembly-language-look-like/33651438#33651438
+Bibliography: https://stackoverflow.com/questions/980999/what-does-multicore-assembly-language-look-like/33651438#33651438
 
 ===== WFE and SEV
 
@@ -10690,6 +10687,8 @@ The Linux kernel wakes up the secondary cores in this exact same way at: https:/
 
 In gem5, CPU 1 starts woken up from the start, so PSCI is not needed. TODO gem5 actually blows up if we try to do the `hvc` call, understand why.
 
+Bibliography: https://stackoverflow.com/questions/20055754/arm-start-wakeup-bringup-the-other-cpu-cores-aps-and-pass-execution-start-addre/53473447#53473447
+
 ===== DMB
 
 TODO: create and study a minimal examples in gem5 where the `DMB` instruction leads to less cycles: https://stackoverflow.com/questions/15491751/real-life-use-cases-of-barriers-dsb-dmb-isb-in-arm

baremetal/arch/aarch64/multicore.S

@@ -39,7 +39,7 @@ cpu0_only:
     /* Wake up CPU 1 from initial sleep!
      * See:https://github.com/cirosantilli/linux-kernel-module-cheat#psci
      */
-    /* Function identifier: PCSI CPU_ON. */
+    /* PCSI function identifier: CPU_ON. */
     ldr w0, =0xc4000003
     /* Argument 1: target_cpu */
     mov x1, 1

baremetal/arch/arm/multicore.S

@@ -20,7 +20,7 @@ cpu1_sleep_forever:
     b cpu1_sleep_forever
 cpu0_only:
 #if !defined(GEM5)
-    /* PCSI CPU_ON. */
+    /* PSCI CPU_ON. */
     ldr r0, =0x84000003
     mov r1, #1
     ldr r2, =cpu1_only