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multicore: remove references to PCSI

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Ciro Santilli 六四事件 法轮功
2018-11-26 00:00:00 +00:00
parent ba2976cc7f
commit 54e15e0433
3 changed files with 5 additions and 6 deletions
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README.adoc
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@@ -10603,10 +10603,7 @@ since gem5 is able to detect when nothing will ever happen, and exits.
When GDB step debugging, switch between cores with the usual `thread` commands, see also: <<gdb-step-debug-multicore-userland>>.
Bibliography:
* https://stackoverflow.com/questions/20055754/arm-start-wakeup-bringup-the-other-cpu-cores-aps-and-pass-execution-start-addre
* https://stackoverflow.com/questions/980999/what-does-multicore-assembly-language-look-like/33651438#33651438
Bibliography: https://stackoverflow.com/questions/980999/what-does-multicore-assembly-language-look-like/33651438#33651438
===== WFE and SEV
@@ -10690,6 +10687,8 @@ The Linux kernel wakes up the secondary cores in this exact same way at: https:/
In gem5, CPU 1 starts woken up from the start, so PSCI is not needed. TODO gem5 actually blows up if we try to do the `hvc` call, understand why.
Bibliography: https://stackoverflow.com/questions/20055754/arm-start-wakeup-bringup-the-other-cpu-cores-aps-and-pass-execution-start-addre/53473447#53473447
===== DMB
TODO: create and study a minimal examples in gem5 where the `DMB` instruction leads to less cycles: https://stackoverflow.com/questions/15491751/real-life-use-cases-of-barriers-dsb-dmb-isb-in-arm