bst_vs_heap_vs_hashmap: use small size by default

This allows us to add it to regressions.

Also clarify that the gem5 run blew up.

README.adoc

@@ -10227,7 +10227,7 @@ To benchmark on the host, we do:
 
 ....
 ./build-userland-in-tree --force-rebuild --optimization-level 3 ./userland/cpp/bst_vs_heap_vs_hashmap.cpp
-./userland/cpp/bst_vs_heap_vs_hashmap.out | tee bst_vs_heap_vs_hashmap.dat
+./userland/cpp/bst_vs_heap_vs_hashmap.out 10000000 10000 | tee bst_vs_heap_vs_hashmap.dat
 gnuplot \
   -e 'input_noext="bst_vs_heap_vs_hashmap"' \
   -e 'heap_zoom_max=50' \
@@ -10274,6 +10274,8 @@ gnuplot \
 xdg-open bst_vs_heap_vs_hashmap_gem5.tmp.png
 ....
 
+TODO: the gem5 simulation blows up on a tcmalloc allocation somewhere near 25k elements as of 3fdd83c2c58327d9714fa2347c724b78d7c05e2b + 1, likely linked to the extreme inefficiency of the stats collection?
+
 The cache sizes were chosen to match the host <<p51>> to improve the comparison. Ideally we sould also use the same standard library.
 
 Note that this will take a long time, and will produce a humongous ~40Gb stats file due to: <<gem5-only-dump-selected-stats>>
@@ -14060,6 +14062,11 @@ That document then describes the SVE instructions and registers.
 
 * LDADD: link:userland/cpp/atomic.cpp[]
 
+Bibliography:
+
+* https://stackoverflow.com/questions/21535058/arm64-ldxr-stxr-vs-ldaxr-stlxr
+* https://preshing.com/20120710/memory-barriers-are-like-source-control-operations/
+
 === ARM assembly bibliography
 
 ==== ARM non-official bibliography