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x86 asm: reorg README to match manual more closely a bit

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Ciro Santilli 六四事件 法轮功
2019-06-16 00:00:07 +00:00
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@@ -12478,7 +12478,7 @@ Vs <<x86-jcc-instructions,Jcc>>: https://stackoverflow.com/questions/6805692/x86
=== x86 miscellaneous instructions
<<intel-manual-1>> 7.3.16 "Miscellaneous Instructions"
<<intel-manual-1>> 5.1.13 "Miscellaneous Instructions"
==== x86 NOP instruction
@@ -12506,6 +12506,41 @@ Generated some polemic when kernel devs wanted to use it as part of `/dev/random
RDRAND sets the carry flag when data is ready so we must loop if the carry flag isn't set.
=== x86 x87 FPU instructions
<<intel-manual-1>> 5.2 "X87 FPU INSTRUCTIONS"
Old floating point unit that you should likely not use anymore, prefer instead the newer <<x86-simd>> instructions.
=== x86 SIMD
History:
* link:https://en.wikipedia.org/wiki/MMX_(instruction_set)[MMX]: MultiMedia eXtension (unofficial name). 1997. MM0-MM7 64-bit registers.
* link:https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions[SSE]: Streaming SIMD Extensions. 1999. XMM0-XMM7 128-bit registers, XMM0-XMM15 for AMD in 64-bit mode.
* link:https://en.wikipedia.org/wiki/SSE2[SSE2]: 2004
* link:https://en.wikipedia.org/wiki/SSE3[SSE3]: 2006
* link:https://en.wikipedia.org/wiki/SSE4[SSE4]: 2006
* link:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions[AVX]: Advanced Vector Extensions. 2011. YMM0–YMM15 256-bit registers in 64-bit mode. Extension of XMM.
* AVX2:2013
* AVX-512: 2016. 512-bit ZMM registers. Extension of YMM.
==== x86 SSE2 instructions
<<intel-manual-1>> 5.6 "SSE2 INSTRUCTIONS"
===== x86 ADDPD instruction
link:userland/arch/x86_64/addpd.S[]: ADDPS, ADDPD
Good first instruction to learn SIMD: <<simd-assembly>>
===== x86 PADDQ instruction
link:userland/arch/x86_64/paddq.S[]: PADDQ, PADDL, PADDW, PADDB
Good first instruction to learn SIMD: <<simd-assembly>>
=== x86 system instructions
<<intel-manual-1>> 5.20 "SYSTEM INSTRUCTIONS"
@@ -12585,33 +12620,6 @@ TODO We didn't manage to find a working ARM analogue to <<x86-rdtsc-instruction>
* https://stackoverflow.com/questions/31620375/arm-cortex-a7-returning-pmccntr-0-in-kernel-mode-and-illegal-instruction-in-u/31649809#31649809
* https://blog.regehr.org/archives/794
=== x86 SIMD
History:
* link:https://en.wikipedia.org/wiki/MMX_(instruction_set)[MMX]: MultiMedia eXtension (unofficial name). 1997. MM0-MM7 64-bit registers.
* link:https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions[SSE]: Streaming SIMD Extensions. 1999. XMM0-XMM7 128-bit registers, XMM0-XMM15 for AMD in 64-bit mode.
* link:https://en.wikipedia.org/wiki/SSE2[SSE2]: 2004
* link:https://en.wikipedia.org/wiki/SSE3[SSE3]: 2006
* link:https://en.wikipedia.org/wiki/SSE4[SSE4]: 2006
* link:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions[AVX]: Advanced Vector Extensions. 2011. YMM0–YMM15 256-bit registers in 64-bit mode. Extension of XMM.
* AVX2:2013
* AVX-512: 2016. 512-bit ZMM registers. Extension of YMM.
==== x86 SSE2
===== x86 ADDPD instruction
link:userland/arch/x86_64/addpd.S[]: ADDPS, ADDPD
Good first instruction to learn SIMD: <<simd-assembly>>
===== x86 PADDQ instruction
link:userland/arch/x86_64/paddq.S[]: PADDQ, PADDL, PADDW, PADDB
Good first instruction to learn SIMD: <<simd-assembly>>
=== x86 assembly bibliography
==== x86 official bibliography