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https://github.com/cirosantilli/linux-kernel-module-cheat.git
synced 2026-01-23 02:05:57 +01:00
arm baremetal: svc, get closer but not there yet
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@@ -19,6 +19,11 @@
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SYSREG_READ(name, type) \
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SYSREG_WRITE(name, type)
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SYSREG_READ_WRITE(uint32_t, daif)
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SYSREG_READ_WRITE(uint32_t, spsel)
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SYSREG_READ_WRITE(uint64_t, sp_el1)
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SYSREG_READ_WRITE(uint64_t, vbar_el1)
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#define SVC(immediate) __asm__ __volatile__("svc " #immediate : : : )
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#endif
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@@ -1,28 +1,34 @@
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#include <stdio.h>
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <common.h>
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#include "common_aarch64.h"
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/* Masks each of the 4 exception types: Synchronous, System error,
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* IRQ and FIQ.
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*/
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SYSREG_READ_WRITE(uint32_t, daif)
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/* Determines if we use SP0 or SPx. Default: SP0.
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* See also: https://stackoverflow.com/questions/29393677/armv8-exception-vector-significance-of-el0-sp
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*/
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SYSREG_READ_WRITE(uint32_t, spsel)
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/* Jump to this SP if spsel == SPx. */
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SYSREG_READ_WRITE(uint64_t, sp_el1)
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void handle_svc() {
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exit(0);
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}
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int main(void) {
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/* View initial register values. */
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printf("daif 0x%" PRIx32 "\n", sysreg_daif_read());
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printf("spsel 0x%" PRIx32 "\n", sysreg_spsel_read());
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printf("vbar_el1 0x%" PRIx64 "\n", sysreg_vbar_el1_read());
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/* Set registers to the values that we need. */
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sysreg_daif_write(0);
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sysreg_vbar_el1_write(0);
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printf("daif 0x%" PRIx32 "\n", sysreg_daif_read());
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printf("spsel 0x%" PRIx32 "\n", sysreg_spsel_read());
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printf("vbar_el1 0x%" PRIx64 "\n", sysreg_vbar_el1_read());
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/* TODO this breaks execution because reading system registers that end
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* in ELx "trap", leading into an exception on the upper EL.
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*/
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/*printf("sp_el1 0x%" PRIx64 "\n", sysreg_sp_el1_read());*/
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/*SVC(0);*/
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/* Should never be reached. */
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/*common_assert_fail();*/
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return 0;
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}
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